Preregistered Workshop Participants
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Downloadable Presentation Files for 2007 KGD Packaging and Test Workshop
Session 1: Technology Overview and Business Issues
Session 4: Enabling Technologies
Pre-Workshop Tutorials
Tutorial #1: 3D Technologies for Die Stacking
Jan Vardaman, Phil Garrou - Techsearch International
Tutorial #2: KGD Testing at the Wafer Level
Memory Devices - Lee Neviill, Micron
RF Devices - Christophe Kelma, NXP
Logic Devices - Jody Van Horn, IBM
Session 1: Technology Overview & Business Issues
Keynote address
Bill Bottoms, Nanonexus
Advanced Packaging: Friend or Foe
Ken Ball, KBTeC
Evaluation, Failure Analysis & Testing Tool List for Die Products in Japan
Tetsuya Onishi, GJ Technologies
SiP Technologies with RF & Mixed Signal Design Challenges & Solutions
CP Hung, ASE
Single Device Tracking - Cost Benefit Analysis
Dave Huntley, Kinesys
Efficient PoP Development and Mass Production Methodology
Young Dae Kim, Samsung
Design-in Requirements for Double-Data-Rate Mobile SDRAMs within Multi-Chip_Packages
Patrick Haibach, Qimonda
Session 2: RF Testing
Speed Testing at the Wafer Level
Wendy Chen, King Yuan Electronics, Co.
7Gbps Loopback Test Modules for KGD
David Keezer, Georgia Tech
Roger Hayward, Cascade Microtec, Inc.
Next Generation Test Requirements for Wafer Level RF Devices
Ken Harvey, Teradyne
Test Set Reduction by Targeting Redundancy Using Statistical Modeling in RF Domain
Martin Margala, University of Massechusetts
WLCSP and On-wafer Probing Test Soultions Using Small-pitch Spring Pins
James Zhou, Antares
Tool for 3D Inspection & Metrology of Bumped Wafers
Pieter Vandewalle
Session 3: KGD Testing
DOE of DRAM Die Thickness vs. Yield and Reliability
Chiate Lin, Inapac
KGD Facilitates a Paradigm Shift in Final Test Manufacturing
Mike Costello & Ching-Too Chen, Star Lab Inc.
Reducing the Cost of KGD Using High Speed Economical Probing Techniques for Diced Die On Stretch Frame
Don Feuerstein, SemiProbe
ESD in Assembly and its Effect on KGD
Jennifer Cheffings, Micron
Session 4: Enabling Technologies
Advanced Packaging and Wirebonding Techniques using X-Wire™ Insulated Bonding Wire Technology
John Persic, Microbonds, Inc.
Advanced Cover Tape Technology for Electronic Component Packaging: 3M Universal Cover Tape (UCT)
James Adams, 3M
Automation in Physical Design: Technology Aware Modeling of 2.5D Sip
Stephan Guttowski, Technical University, Berlin
Ionic Migration Behavior in Fine Pitched Wiring on Flexible Substrate for Flat Panel Displays
Yuje Kimura, Kogakuin University
Session 5: KGD Engineering
Capacitive Coupling Interconnections for 3D System Integration
Roberto Canegallo, STMicroelectronics
Presentation
Current Challenges in Preassembly: The Focus Changes from Thinning to Singulation
Franco Mariani, Infineon Technologies
Presentation
Development of Fine Pitch Wire Bonding Using Electroless Ni-P and Au Plating on Al Pad
Norihiro Togasaki, Toshiba
Presentation
Process Control Monitor Testing for Integrated Passive Device Wafers
Wong Kok Sun
Presentation
Ultrasonic Flip Chip Bonding to Organic Substrate
Takatoshi Ishikawa, Panasonic Factory Solutions Co., Ltd
Presentation
Electrical FA Challenges for KGD
Tony Hallan, Micron
Presentation
Final Testing of Digital SiPs Through Reuse
Frans de Jong, NXP
Presentation