Previous Workshops: 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007
2001 Workshop Technical Program
Session 1: Die Products Industry Overview
Session Chairs: Paul Wakefield, National Semiconductor & Mike Roughton GoodDie program
1.1 SOC vs. SOP - which is the technology of the future PDF (4.9 MB)
Rao Tummala, Georgia Inst. of Tech.
Rao stated that SOC is the most pursued technology but may not lead to a complete system. SOP is more cost effective as one can optimize the best of IC's in a package for the best-cost effectiveness. SOP can also optimize functions between the IC's and the package and also has a faster turn around and time-to-market.
The new technology CMM (convergent microminiaturized microsystems) will be driven to have 1 billion transistors on a chip, from the 1µm technology 10 years ago to in the future 0.01µm technology i.e. 10psec to 1 psec, and the aim is now also for a 400mm wafer. Examples of CMM include video cell phone, cellular phone/watch, wearable computer and medical implants. Other technologies now becoming available include CMOS with copper, SOI and SiGeBICMOS. SOC is limited by using such technology at present, however when embedded RF can be used by 2007 SOC may be the better solution.
1.2 Die Products market in Europe PDF (.4 MB)
Francisco Ibáñez, European Commission
In Europe ST Microelectronics, Infineon and Philips are the top ten world IC producers taking about 21% of the European market share. In 2000 the market size was $42B with a growth rate of 32% giving in 2001 $249B (22% world production). Main application areas are auto, telecom, EDP/PC's and consumer with volume growth drivers of set-top boxes, mobile, smart cards and GPS. The future is to create an ambient intelligent landscape with user friendliness tailored to needs that can be recognized and anticipate the desire of the users. The main requirements are for ultra high performance, high bandwidth, small form factor, low power, low cost devices and user friendly this being the ambient intelligent vision.
1.3 Die products markets, Asia Pacific PDF (.4 MB)
T Onishi, Grand Joint Technology Ltd.
Technologies used in the Far East include wire bonding Au and Al (30%) and flip chip using solder, ACF, NCP, Au and AuSi. These being on such substrates as PCB, COG, COF and COB. Flip chip bonding is mainly on organic substrates with ACF technology now being used. COB trends are for toys, music card, PDA , phone, display module etc. Wire bonding uses machines with rotating stage or head with bond pitch down to 65µm. Plasma cleaning is often used prior to assembly. Bumpless TAB is now also being used for ILB. Already available in the Japanese market are colour displays for mobile phones.
1.4 Latest ASET activities for system integration R & D in Japan PDF (1.9 MB)
M Ishino, ASET
The issue of ESI, Electronic System Integration includes shortening electrical wiring, replacing wiring with optical and reducing EMI. The market is expected to increase 10 times in 10 years. By stacking die area can be reduced by one tenth to give 1Tbps. The three targets will be approached by chip thinning to enable 10µm diameter through vias 70µm depth and plating up with Cu. Back grinding to 55µm to reveal Cu pillars and then multilevel stack so 4 chips will be 200µm high with Cu pillar interconnect. Optical transmission is aimed for up to a distance of 100m which will also enable the reduction of EMI. At the present stage the Cu pillar stack is being developed and evaluated.
1.5 Worldwide die product markets PDF (.7 MB)
Jan Vardaman, TechSearch International Inc.
The four areas for bare die are flip chip, wafer level packages, COB and TAB. The main focus is on flip chip with the drivers of performance and form factor. This is for devices such as uP, ASIC, DSP, chip set, SRAM RF drivers etc. and applications such as mobile phones, camcorders, driver IC,s for displays, automotive etc. Array flip chip gives the highest pin count and performance compared with other technologies. Over 20 companies worldwide can now wafer bump with solder or gold with costs in the order of $40/6inch Au wafer. Applications include FCOB for a Delphi on-engine module, a Seagate disc drive module and Ericsson's Bluetooth module. The Pentium III is now also flip chip. By 2005 it is forecast that 3500 million units will be made by using FCIP & FCOB . Wafer level packaging is mainly aimed at low pin count devices, <50, for such components as EEPROM's, integrated passives, voltage regulators, power amplifiers and medical devices.
1.6 Die supply in a post hybrid age PDF (.2 MB)
Ken Ball, Eltek Semiconductors Ltd.
Originally bare die were supplied for the military, aerospace and space flight quantities in small quantities, but also at high cost and often with added value testing by mainly chip houses. Now the industry has changed where the commercial market requires very large quantities of bare die for such applications as automotive, telecom, smart cards, etc. with quality levels of <4ppm but at very low cost. This requirement can be supported by the semiconductor foundries due to the large quantities but for prototyping and other applications, the high rel. market still being there, it is now very difficult to obtain bare die. If they are available the price is high and there will also probably be poor support from the vendor as they lose interest with the low quantities. So in general the foundries will not support the low quantities and the chip houses will but at a premium cost.
Session 2: Future trends toward System in a Package
Session Chairs: Jan Vardaman, TechSearch & Barbara Vasquez, Infineon
2.1 Stress engineered metal interconnects PDF (.6 MB)
David Fork, Xerox.
This paper described a method of creating self assembled springs on a wafer so that test and assembly can be carried out to a number of substrate types without the further edition of wire bonds etc. Every chip can be tested before assembly, on the assembly station or at wafer stage. The contact springs are made by using the differential stress properties in materials during the deposition stages onto the wafer. Typical materials used are sputtered Mo-Cr which when etched appropriately a spring bends away from the surface of the die to form the contact material. Over 10,000 thermal cycles between 25°C and 125°C have been achieved with no failures. Springs of 16-55µm high on a 22µm pitch have been made.
2.2 Die products standard activity
Jim Wolbert, Chip Supply
With the successful completion of the completion and issue of the CECELEC Specification ES59008 "Data requirements for semiconductor die" in Europe this document has now been put forward as the basis of an International standard to the IEC. Three meetings have now been held with participants from the USA , UK, Japan, Germany, Belgium, Holland and Switzerland who have proposed an IEC Standard 62258 "Semiconductor die products - Minimum requirements for procurement and use". This will cover such areas as mechanical requirements, test, quality, handling, electrical and thermal simulation and particular die types such as bare die, flip chip and CSP etc. There will also be a section on electronic data transmission.
2.3 Technologies and trends in wafer level packaging
PDF (3.7 MB)
Curtis Zwenger, Amkor Technology
This presentation indicated that most processing is now taking place at the wafer level with pitch of 0.5mm on area arrays. Flip chip is now showing a very high growth rate with now 1000 cycles of -65°C to 150°C being the expectations with no failures. Also reliability without underfill is required. Some of the major developments are now being carried out in Japan with examples of the various technologies being described.
2.4 Minimalist type packaging using un-bumped die and bumped substrates PDF (5.9 MB)
Bob Betz, Delphi Connection Systems
Current drivers are cell phones and low cost. To achieve this various snap cure adhesives are being evaluated which have already passed 1000 hours 85 %RH/85°C and 1000 cycles -40°C to 125°C. 20-30µm bumps on 65µm pitch of various geometry's on the substrate are being evaluated. These are aimed at penetrating the adhesives to contact the die.
2.5 Trace method for die products PDF (.5 MB)
Jerry Secrest, Secrest Research
Die marking equipment can be as much as $500k with a production rate of 10/15 wafers per hour. Various techniques are available including inking, wafer mapping when electrical testing, backside printing and laser marking. Whether die and wafer tracing is required is dependant on the application and what are the returns to be gained after the investment has been made. Thus the type of traceability required is dependant on product volume, status, product, application, die process etc.
Session 3: Wafer Test methods and reliability screens
Session Chairs: Jody Van Horn, IBM & Jim Rates, Chip Supply
3.1 Test technology trends for high density packages
Yervant Zorian, LogicVision
It was indicated that in 1999 345M SOC (Single Chip Packages) were manufactured and that by 2004 this will rise to 1.3B units. For this test cores used should be self contained also and especial in respect to test. A problem then is to have a standard core test interface; standardization is going on IEEE P1500 SECT, started June 1997. A wrapper is used for packing / control the core test. Test cost start getting as high (higher) as production cost. The BIST approach is helping out of this, becoming the trend towards high density and making BIST cheaper but the testers more expensive. Dynamic faults have a growing influence making it necessary to do at speed test. The memory fraction in logic ICs is increasing from now (50%) to 96% by 2014. Embedded test provides for a faster time to market and volume and cost reduction.
3.2 Test-in-pocket precision carrier tape? A new approach to testing bumped devices PDF (.4 MB)
Heather Kiffe, 3M
This paper was based on the development of a carrier tape, in co-operation with Atmel, to test flip-chip die in the tape so that they can be rejected prior to assembly on the pick and place machine. The tape has a window in the bottom to allow clean access to the solder balls on the device. It was also found that <5°rotation is permissible in the pockets to test the devices which is less than the 20° allowed in current standards. The ability to the cover tape had also to be allowed so that defect devices could be removed. Polycarbonate was chosen for the tape to allow precision forming to take the die and to stand assembly temperatures and have low shrinkage.
3.3 Cost comparison of wafer-level versus singulated die burn-in and test PDF (2.4 MB)
Steve Steps, Aehr Test Systems
This presentation pointed out that 20-30k probes were required to test a whole wafer compared with a single die test burn-in station. It was shown that for a 2 hour burn-in for a typical die CSP was the most expensive approach compared with wafer prober, carrier (such as DiePak) and wafer level burn-in and test. However for a 24 hour burn-in a technique such as Die-Pak as the cheapest with WLBT, CSP and wafer probe being in ascending order of cost. However this always depends on the size of the wafer, the complexity of the die, the reliability required etc.
3.4 Development of the probing for technology to 20µm pitch electrode PDF (1.2 MB)
Kenji Takahashi, ASET
This is a technology to develop four 50µm chips stacked with 20µm pitch pads. Finger leads (GSC) with pin diameter of 10µm were chosen as opposed to silicon whiskers. Si whiskers were tried but the pin positions were not accurate enough. Also they were found to fatigue after approx. 10 cycles. Even so it was found that 40µm overdrive of the GSC technique was found to be necessary to obtain good contact for accurate testing. Development is still undergoing.
3.5 Recipe for reliability in wafer level packaging PDF (3 MB)
Scott Lindsey, FormFactor
This paper was a further evaluation of the development of the MicroSpringTM for the testing of wafers at wafer level etc. It has been shown to be cost effective for a memory package of more than 300 dice per wafer. Impedance is 0.8 nH at typical 800 µm spring length. It is completely compatibility with standard SMD mounting and down to 300 µm pitch possible. It is also convenient for higher values than 500 µm area pitch. MOSTTM (µSpring) technology delivers as much cycles (TC) than any QFP. It is lower cost for chips that provide area array pads, because it leaves out one process step.
3.6 Sacrificial metal wafer-level burn-in and test challenges PDF (1 MB)
John Stroupe, Consulting for Motorola
This was an 8 inch wafer WLBI method using a deposit, pattern and etching for sacrificial metal, allowing for BI contact and after this removal of the metal. Motorola has been using this technology since 1995. At 200 die per wafer WLBI and package BI is same cost. The more dice per wafer, the cheaper the process is going to be.
3.7 Wafer probe tests and stresses used for quality and reliability improvement PDF (1 MB)
Art Wager, Reliability Consultant
This paper summarised various wafer level test procedures to obtain an approach to KGD. Such comments form the paper included: IddQ measurements . Ave 1.7 mA. Low voltage tests (LVT). Defect basics with distributions were shown. LowVT - high performance - high leakage - no IddQ. Back bias on N and P wells -> 10x Idd leakage reduction. Physical analysis has yet to be done. This work is being carried out in conjunction with the DPC. (Die Product Consortium)
Special Session: Chip on board tutorial PDF (6 MB)
Tetsuya Onishi, GJ Technology
This session was mainly composed of the methods used for Chip-On-Board technology in Japan and China. It was stated that in Japan mainly Au wire bonding was used for COB whereas in China Al bonding was used due to reduced cost, at least two times. PCB substrates usually had an Au/Ni/Cu finish suitable for Al wire bonding. Flip chip was also used using ACF as well as Au-Sn and solder assembly. The various assembly techniques were also illustrated such as automatic Al and Au wire bonding. Farious analysis techniques were used for the PCB assemblies including X-ray florescence for plating thickness on PCB's and the Omega meter technique for contamination on PCB board in µg/sq in where 0 was excellent and <3 good. SEM analysis was also carried out in Japan but not China. Epoxy encapsulation was used as the final process for COB technology. Typical applications were: watch, E-game, toy, calculator, clock, PDA, pager, LCD module, scanner, telephone etc.
Session 4: Substrate and Module level test
Session Chairs: David Keezer, Georgia Tech & Bruce Kim, ASU
4.1 Future of test for SIP PDF (2.7 MB)
Paul Wakefield, National Semiconductor
This presentation explained the various test strategies for the future of the SIP. This included the IEEE test standards which were: IEEE 1149.1 Standard for boundary scan test; IEEE 1149.4 Mixed signal test standard: IEEE 1159.5 Module test and maintenance bus and IEEE P1532 Standard for boundary-scan -based in system configuration of programmable devices. However, it was pointed out, that all these techniques for test need further real estate on the device and extra pin outs, e.g. 5 for digital and 7 for analog/mixed signal, to be able to carry out effective testing.
Session 5: Flip Chip and associated assembly and handling
Session Chairs: Charles Gutentag, Tempo Electronics & Ken Ball, Eltek
5.1 Plasma cleaning application for stacked package and flip chip bonding PDF (.8 MB)
Dr. Hiroshi Haji, Kyusyu Matsushita
This paper demonstrated that solder ball joint strength decreased with increased gold thickness however wire bonding strength increased in a combined assembly solution for BGA etc. It was found that if the Au thickness was reduced to increase the solder ball joint reliability the Ni in the electroless Au inhibited good wire bonding. However if plasma cleaning was used prior to wire bonding the reliability of the wire bond joints could be increased dramatically without affecting the reliability of the solder ball joints.
5.2 Flip chip ACF
Peter j Opdahl, ITO America
The use of ACF has now been shown as a viable technology for semiconductor assembly. One of the main applications is for flat panel displays with Si die on a glass substrate with 99.9%+ yields being achieved with pitch of joints is down to 40µm. The technique is used in Asia for cell phones, PDA and HD semiconductors. Anisotropic conductive adhesive techniques now have cycle times for bonding of 5-15 seconds using 3-7µm size coated polymer particles with Au/Ni. These are now shown to be more effective than using non compression methods such as C4, stud bump, ultrasonic etc. which all use underfill whereas ACF acts as its own underfill.
5.3 Stacked flip chip CSP development PDF (.8 MB)
Paul Hoffman (David Zoba), Amkor
This presentation described the experience at Amkor on using stacked die and the improved performance due to the short current path. Effectively the base die acts as a substrate and has wire bond pads to connect to a carrier. On top of this one can have pads for a flip chip array with up to fore die on top.
5.4 Bare-chip bonding technology for consumer electronic device PDF (.6 MB)
Mitsuru Chino, Misuzu
The trend is now that flip chip bonding will have changed to Sn/Ag solder by 2003. Also other technologies will be in greater use such as ACF, stud bump bonding and Au-Sn diffusion bonding. The latter has been tested for 1000 cycles -65°C to 150°C with 0/27 failures and 1000 hours 85%RH/85°C load biased 0/96 failures. Stud bumping will be mainly used for flip chip die <100µm. Problems using ACF have been solved using a Teflon tool. Thinner die and 3-D stacking with up to 4 die in a stack of 1.4mm thick are now being used.
5.5 Flip-chip BGA with high Cte glass ceramics carrier PDF (.7 MB)
Ryusuke Oota, Fujitsu
This paper described the use of glass ceramic substrates for a 40GHz application target. The glass ceramic substrate had 10 layers forming a high I/O package of 2116 pin out. The substrate was found to have the highest reliability and performance compared with PTFE and organic build up substrates . It also had great high routing flexibility. It has also passed the standard thermal cycle/shock, temperature store, humidity tests.
5.6 Turnkey flip chip assembly solutions PDF (1.8 MB)
Andrea Chen, Siliconware USA Inc.
This presentation described a wafer bumping service which at present will cater for 200mm wafers and shortly 300mm wafers. Siliconware are the third largest packaging sub-contractor in the World and provide similar services to Amcor. Full reliability tests have been carried out on their bumped wafers and this covers both peripheral and array bumping.
Session 6: Technologies supporting System in a Package
Session Chairs: Georg Meyer-Berg, Infineon, Jim Wolbert, Chip Supply
6.1 Integrated solution for high resolution inspection and die sorting PDF (1.1 MB)
Scott Evans, Laurier Inc.
CSP is the big driver for the use of bare die particularly for wafer level packaging. Standalone visual inspections have faults particulary whin applied to such packaging to find defective die. Laurier have now developed an integrated visual inspection using a vision system from STI which is built into the assembly pick and place machine so that it does not slow down during the assembly process while identifying the defect components. This system is computer controlled and does not depend on the operator.
6.2 Recent inovations for System-in-Package and multi-chip modules PDF (1.6 MB)
Andrea Chen, Siliconware USA Inc.
This paper compared the advantages of SOC (System on a Chip) compared with SiP (System in a Package). However in the long term it was shown that SiP has better performance that SOC due to higher yield, smaller form factor, enhanced electrical performance and lower overall cost. A road map for SiP to 2002 was shown showing the various assembly methods for manufacture of various types of SiP.
6.3 MCM's in cost-driven applications: callenges and solutions PDF (.4 MB)
George Grenley, Strand Interconnect
This paper described a cost effective MCM technology for a microcontroller for a television. The device contains two die (microcontroller and flash) on a silicon substrate with conventional Au wire bonding in a lead frame package. The Si substrate contained two Al metal tracking layers with BCB dielectric. 200mm wafers were used to manufacture the substrate. It was found by analysis to be more cost effective than BT PCB, HTCC and LTCC.
6.4 System in a Package (SiP) technology options and applications PDF (1.2 MB)
Marcos Karnezos, ChipPac Inc.
This presentation described various methods of assembling SiP using stacked die. Examples were flip chip die with upto 1.5mm overhang wire bond die on top and two wire bond die the top one being 250µm smaller than the bottom one. Au stud bump could also be used for flip chip due to lower cost. Current challenges include thinner die 50-140µm, thinner laminate substrates, Cu pad wire bonding, KGD and system level reliability over riding package level reliability.
6.5 System in Package manufacturing line PDF (4.9 MB)
Paul Hoffman, Amkor Technology
Amkor manufacture 16 million per year SiP packages. Typical examples of this technology include memory cards, RF and wireless, image sensors/cameras, networking and computing. The benefits are size reduction, improved system performance, can change subsystem without costly changes to system board and can standardize subsystem packages. SiP has now become a readily acceptable packaging solution which is more complex than standard packaging. The main drawbacks are substrate supply in quantity and design tools, but even so, this is a very large growth area in the industry.