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The 2009 KGD Packaging & Test Workshop will be hosted by SEMI on October 1-2, 2009. Please visit the SEMI KGD Workshop site for updated information. This site is maintained as an archive for past workshops.

Previous Workshops: 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007

2002 Workshop Technical Program

Session 1: Die Products Industry Overview

Session Chairs: Paul Wakefield, National Semiconductor & Larry Gilg, Die Products Consortium

Opening Remarks
Sherb Bridges, National Semiconductor & Ara Talaslian, Hyperchip

Keynote Address PDF (3.5 MB)
Jan Vardaman, TechSearch International

Latest ASET Activity for System-Integration R & D in Japan PDF (1.1 MB)
Manabu Bonkohara, ASET

Die Products Markets in Europe PDF (1.7 MB)
John Campbell, Analog Devices

Die Products Markets in Asia/Pacific PDF (3.6 MB)
Tetsuya Onishi, GJ Technologies

Die Products Markets in the USA PDF (.4 MB)
Larry Gilg, Die Products Consortium

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Session 2: Future Trends in the Portables World

Session Chairs: Jan Vardaman, TechSearch International & Tetsuya Onishi, GJ Technology

Analysis and Countermeasures for Thermal Expansion Under the Sub-micron LD Assembly by Passive Alignment PDF (6.6 MB)
Tatsuo Nagamatsu, Arai Yoshiyuki, Toray Engineering Co. Ltd. Japan

Obsolescence: Compressed Product Life-cycles Create Opportunities for Commercial Die Banking PDF (.7 MB)
Mike Roughton, GoodDie Network

Semiconductor Assembly Council (key performance indicators (yield, ppm, cycle time, etc.) by package families) PDF (.2 MB)
Marla Cooper, Semiconductor Assembly Council

Laser Drilling of Microvias in silicon and Other Materials PDF (2.2 MB)
Dr. Adrian Boyle, Xsil

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Session 3: Wafer Test Methods and Reliability Screens

Session Chairs: Jody Van Horn, IBM & Walid Ballouli, Motorola

Reducing KGD Test Cost Via “Prediction” Testing PDF (.2 MB)
Jerry Secrest, Secrest Research

True IDDQ Test and its Real-life Application PDF (.6 MB)
Hans Manhaeve, Q-Star Test NV

Ultra Fine Pitch Probing Technology PDF (1.7 MB)
Michinobu Tanioka, ASET

An Integrated Solution for KGD-- At-speed Wafer-level Testing and Wafer-level Burn-in PDF (.9 MB)
An-Hong (John) Liu, Yuan-Ping (Noty) Tseng, ChipMos

Alternatives for Producing Burned in and Tested Die PDF (1 MB)
Steve Steps, Aehr Test Systems

Wafer Level Test and Burn-In PDF (1 MB)
Steve Martinez, Tokyo Electron Unlimited

Cost Comparison between Sacrificial Metal Wafer Level Burn-in and Test (SM WLBT) vs. Package Burn-In and Test PDF (.3 MB)
Walid Ballouli, Teresa McKenzie, Motorola

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Session 4: Substrate and Module Level Test

Session Chairs: David Keezer, Ga Tech & Bruce Kim, ASU

Current Progress of a Low-cost Parallel Test Methodology for Passive Validations and Interconnect Verifications for SoP Development PDF (.1 MB)
Kimberly Newman, University of Denver

An FPGA-Based Digital Logic Core for Embedded Test Applications PDF (.7 MB)
D.C. Keezer, J.S. Davis, Georgia Tech

A Real-world Application Used To Implement A True IDDQ Based Test Strategy (Facts and Figures) PDF (.6 MB)
Hans Manhaeve, Q-Star Test NV; Joseph S. Vaccaro, Loren Benecke & David Prystasz, Motorola

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Session 5: Die Products Infrastructure

Session Chairs: Jim Rates, Chip Supply & Peter Opdahl, Ito America Corporation

Post – A novel, Lo-cost,Lo-stress, Flip-chip Technique For Existing Device PDF (.7 MB)
Elwyn Wakefield, Mintech Semiconductors, Ltd.

High Pin-count Ultrasonic Flip-chip Bonding and Plasma Cleaning Technology PDF (3.1 MB)
Ryota Furukawa, KME Panasonic

Development of Fine Pitch Flip Chip Bonding Technology for COF (Chip on Flex) PDF (.6 MB)
Mitsuru Chino, Misuzu Industries

Long Time, High Volume MCM and KGD Product Manufacturing Report PDF (2.3 MB)
Georg Meyer-Berg, Infineon

Solder Joint Reliability of Wafer Scale CSP Package PDF (1.5 MB)
Bob Sullivan, HDPUG

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Session 6: Multichip Packaging


Session Chairs: Russ Wagner, Rockwell Collins & James Forster, Texas Instruments

Socrates – MCM based Symmetric High Bit Rate Digital Subscriber Line PDF (2.8 MB)
Georg Meyer-Berg, Infineon

Die Products Application Study PDF (2.3 MB)
Chris Windsor, Portelligent

Super High Density Interconnect PDF (.8 MB)
Mario Aguirre, Fujitsu Microelectronics America

Gold Dot Applications for the Portable World PDF (3.6 MB)
Bob Betz, Delphi Connection Systems

Quality Issues in Automotive Electronics PDF (.1 MB)
Wolfgang Mackrodt, Bosch Electronic

Concluding Remarks

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