Previous Workshops: 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007
2002 KGD Workshop Summary
The workshop kicked off with a session on Die Products Markets. Jan Vardaman of Techsearch International gave the keynote address “Bare Die Comes of Age” in which she highlighted the various applications and technologies that are seeing increased die usage. Ms. Vardaman stressed that all aspects of the die products value chain are being developed in China, from semiconductor fabrication to advanced packaging and assembly though EMS providers. International and domestic companies expanding COB assembly operations include Group Sense, Kinpo, Namtai, SAE Magnetics, Saitek Electronics, and Wong’s Electronics.
A mainstay session for the workshop over the past several years is an update on the development of wafer level burn-in and Test(WLBT). Presentations made on WLBT development at past workshops have focused on the developmental nature of the technology. This year’s presenters, Aehr Test Systems, Tokyo Electron America (TEL), ChipMos and Motorola all detailed their production processes and equipment. Steve Martinez of Tokyo Electron America discussed his company’s collaborative effort with Motorola to develop a production wafer level burn in and test tool. The approach relies on built in self test (BIST) to reduce the number of connections to the DUT, according to Martinez. The system can provide burn-in stress to 512 die per wafer, 7 wafers per cell and 4 cells per system, for a total of over 14,000 die being burned-in and tested in parallel with temperatures up to 150C. The liquid cooling of the production system can realize up to 1200W of thermal dissipation for a 200mm wafer and maintain a temperature gradient across the wafer within 5C at 300W. The WLBT process replaced three test insertions for the production flow for a PowerPC device. Motorola is developing this technology along with the production use of the sacrificial metal method of wafer level burn-in, as reported by Walid Ballouli. Again, Mr. Ballouli highlighted how the WLBT system reduces the number of test insertions, the amount of fixturing needed to support a product and detailed the savings in floor space created by the WLBT system.
Another significant development outlined at the workshop was the definition of a new paradigm for KGD test and inspection. Dan Nelson of August Technology led a panel discussion of the ideas behind merging wafer test and inspection of die on film frame. Short presentations from suppliers of equipment (Electroglas, TEL) and users (Analog Devices, International Rectifier) preceded an audience Q & A session to explore the costs and benefits of this final manufacturing approach. The Die Products Consortium is developing a project to provide more information to its members regarding this technology.
Several interesting presentations on applications rounded out the workshop. Chris Windsor compared IC packaging metrics in cell phones past and present. Die products are being adopted in several guises in the cellular world, including flip chip ( or wafer level csp), chip on flex and especially in stacked packages. Stacked package innovations are being quickly adopted in the cell phone world, where compact size and expanded functionality are at a premium. Mario Agurrie of Fujitsu Microelectronics America detailed his company’s development of an 8-layer chip stack, which has been qualified at FMA today.
Plans are already underway for next year’s workshop, to be held on September 8 – 10, once again in Napa, California.