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2003 Workshop Technical Program
Session 1: Business Issues & Worldwide Markets
A Semiconductor Packaging Forecast PDF (.3MB)
Morry Marshall, Semico Research Corporation
Morry Marshall, VP Strategic Technologies, Semico Research Corp., will present Semico's outlook for semiconductor packaging sales and a discussion of an opportunity for increased SiP (System in Package) packaging sales in horizontal markets. This presentation will begin with Semico's forecast for total worldwide semiconductor sales and semiconductor packaging sales. The presentation will then describe the forces creating an opportunity for SiPs to replace SoCs (System-on-Chip) and offer suggestions about what needs to be done to realize the potential. Semico is a market research company focusing on the semiconductor industry and closely related industries. Semico believes that semiconductor packaging is a strategic factor in the growth of semiconductor sales.
Future Trends and Development, MEMS and KGD PDF (4.9MB)
Jim Walker, Gartner-Dataquest
MEMS technology is in a transition phase. From the present-day technology of sensor-based functions, the new world of MEMS creates miniature motors, gears, gyros and pulleys, all combining to form sophisticated and complex microsystems. These new applications and technology for MEMS will direct new requirements on semiconductor wafer level packaging and assembly. These advances will result in many real and other perceived market opportunities. This presentation will examine where the MEMS industry is today, where it will be in the future, and how it might get there with the continuing development of known good die and wafer level packaging.
Stacked CSPs: Market and Technology Developments PDF (1.9MB)
E. Jan Vardaman, TechSearch International, Inc.
With increased demand for small form factor packages for mobile phones, there is a need for dense packaging. Stacked chip scale packages (CSPs) are targeted at mobile phones, PDAs, and other portable product applications. Future applications will also include memory cards and data storage applications. The first volume stacked CSPs contained flash and SRAM to make a two-die stacked package. Today's stacked die packages contain more than two-memory die and sometimes contain logic devices such as ASICs or DSPs. Challenges in the growth of stacked die packages include wafer thinning and the ability to stack known good die. This presentation will address the drivers for stacked packages, emerging technology for wafer thinning, die stacking, and test.
SiP Developments: A Company Strategy and Perspective PDF (1.3MB)
Georg Meyer-Berg, Infineon Technologies
Infineon is focused on delivering system solutions for our customers. This is enabled by our broad range of skills and big technology portfolio. The bigger the (sub-) system is, the broader the range of required technologies, making the classical system on chip approach more difficult. While it still has its role, the added focus is on System-in-Package (SiP), where we gained considerable experience during the last 10 years. With more and more of these projects, our demand for KGD is increased and we're encouraged to deliver KGD ourselves. Further enhancement for SiP is currently in progress. A low cost chip-to-chip interconnect technology allowing 30 µm area pitch contacts will be shown and a special semiconductor technology for integrating RLC networks into SiPs.
Session 2: Advanced Packaging
3-D Packaging: Stacked-Die and Stacked-Package PDF (1.3MB)
Marcos Karnezos, ChipPAC, Inc.
Three dimensional (3-D) package level integration provides the smallest footprint in a thin, light module that can run at higher speed, consume less power, and cost less than the alternative assembly of these individual packages on a mother board. The expectation is that these modules will meet the standard package reliability specifications and be assembled using established infrastructures.
The primary limitations of 3-D packages are final test yield and the total profile thickness determined by the end application. Given that final test yield depends on the individual die or package yields and the final module assembly yield, pre-tested dice or packages are highly desirable. Probed good die in wafer form are available in volume but the final test yields vary widely depending on the maturity, technology and design complexity of the chip. Tested good packages are widely available but are not readily stackable in a 3-D structure.
Examples of both Stacked-Die and Stacked-Package modules currently in production will be described with technical details and reliability results. A novel Package-in-Package (PiP) module currently under development and targeted for cell phone applications will be introduced, and the package structure, design principles and assembly process will be described.
Optimized Stacking of Bare Die and Chip-Scale Packages
Jeffrey Demmin, Tessera, Inc.
System requirements for high density packaging have driven the development of both bare die stacking and package stacking technology. Die stacking creates the smallest possible footprint and, in some cases, can be the lowest profile. However, this approach can create many challenges, including gaining access to bare die from potential competitive sources, as well as procuring known good die (KGD) to minimize the impact of compound yield. Package stacking can address the test and KGD issues by allowing straightforward testing of packaged components before they are stacked. However, there can be size and performance penalties depending on the package stacking technology and design methodology.
The optimized solution for multi-die integration is often a combination of bare die and package stacking. The best approach depends upon the die sizes, number of die to be combined, bond pad configuration, interconnectivity, yield and cost, as well as the cost and yield associated with the packaging and test processes themselves. It is possible to evaluate the different options in a systematic way, as illustrated with Tessera's multi-die chip-scale packaging technology, in which bare die and/or packaged chips can be integrated into one small form factor solution.
Development of Tape-Stacked Coreless Substrate PDF (.5MB)
Jun Onohara, Toppan Printing Co., Ltd.
A chip size package (CSP) and a fine pitch ball grid array (FBGA) as semiconductor packages have attracted much attention. We have developed a reel-to-reel consecutive manufacturing process for a tape-stacked coreless substrate composed of multi conductive wiring layers (minimum four layers) with ball grid allay connections (Multi layers Tape-BGA). The benefits of this substrate are; (a) it is very thin (150um in the case of four layers), lightweight and applicable to a large number of pin counts (up to 2000), compared to that of the conventional substrates; (b) the realization of fine conductive wiring with a high accuracy in both width and thickness; and (c) low production costs. Furthermore, small tolerances in insulating layer thicknesses, and wiring widths and thicknesses make it easy to control the characteristic impedance. Possible stacked via structure facilitates the wiring pattern design rule. These features provide a substrate that meets recent requirements of ultra high speed signal transmission.
Wafer Level Process of Redistribution of Wire Bond Locations
Gusung Kim, Samsung Electronics Co., Ltd.
Wafer Level Chip Scale Package (WL-CSP) is one of the major products within the Known Good Die business. This true chip-size package is fundamentally based on wafer level process technology, which forms redistribution lines. The redistribution line process now applies to a variety of applications.
Center I/O designed Die is the common chip layout due to improvement of the signal distribution's performance. It is also beneficial to reduce a chip dimension comparing Edge I/O designed Die. However, Edge I/O designed Die is still useful to organize a System-In-Package. The redistribution process is a wonderful candidate to overcome a design limit for Edge I/O designed die. The redistribution line is connected with the center I/Os to the Re-designed edge I/O for allowing a wire bonding interconnection.
Redistribution wire bonding lines will be introduced, with emphasis on the manufacturing process and applications within Samsung. In addition, Samsung's approach to the Known Good Die business will be presented.
Au Bumped IC Flip Chip Bonding for LCD Module Application PDF (1.5MB)
Tetsuya Onishi, Grand Joint Technology Ltd.
This presentation addresses the following topics:
- General & LCD module trend
- Bonding method
- ACF bonding and process control
- Au - Sn Bonding & Ultra Sonic bonding
- Bonding Pitch
- Substrate
- Bumped IC
Pre-Applied Underfill Process for COF (Chip on flex) PDF (.7MB)
Misuru Chino, MISUZU Industries Co.
We developed a pre-applied underfill process for flip chip bonding COF (Chip on Flex). This process will meet the demands for finer pitch bonding, expansion of applications and cost reduction. The key feature of the pre-applied underfill process is applying underfill resin before Au/Sn diffusion flip chip bonding on flex substrate.
Key points of this technology:
(1) Development of high boiling point underfill resin over Au/Sn diffusion bonding temperature, about 300 degrees C.
(2) Establishment of the voids elimination process by post curing and the optimizing condition of resin reaction rate. After Au/Sn bonding, 40-50% of voids eliminated by post curing.
(3) Saving the investment for equipment and reduce the process time by the bonding process uniting with underfill.
In this paper, we describe this new flip chip process, the detail of bonding mechanism, the requirement for bumped bare chip IC & the substrate and interconnection reliability test results.
Session 3: Novel Processes & Materials
General Flip Chip Bonding Techniques and Processes PDF (.1MB)
Henry Chou, Besi Die Handling
This presentation is a general overview of flip chip bonding techniques and bonding processes associated with flip chip and die attach. Bonding techniques will cover two methods: non-contact bonding and contact bonding. The bonding process discussion includes five die attach process categories that are broken down further into specific applications.
Excellent Reliability and Stand Off Height of Plastic Cored Solder Ball PDF (.9MB)
Nobuyuki Okinaga, Sekisui Chemical Co., Ltd.
Recently, BGA and CSP are employed as area array connection methods. Most of them are connected with solder bump, much like a solder ball. However, there exisists a large CTE mismatch between the different constituent substrates and chips. As a result, the solder joints are easily broken by thermal strain, causing low reliability.
To ameliorate this problem, we have studied various ways to relax the thermal stress. We have developed solder ball made of a compliant plastic core. The Young's Modulus of the plastic core is much smaller than that of metal, so it is superior in relaxing the thermal stress. The result of temperature cycle tests showed that it had excellent reliability and enabled much greater resistance to micro-cracks in the solder layer than conventional solder balls. In addition, it is superior in keeping stand-off height exactly between upper and lower substrates, because the particle diameter of the plastic core is very uniform.
Laser Micro-machining Tools and Processes for High Volume Semiconductor Manufacturing
Dick Toftness, Xsil USA
Today's advanced laser technologies are employed in FAB and backend manufacturing processes to improve yield, performance, throughput and resolve issues critical to the dicing of Low-k wafers and thin wafers, as well as the creation of interconnects in silicon and various emerging wafer level package materials.
The presentation gives examples of improvements in die break strength, faster dicing on thin silicon, and increased throughput for the low k materials. This advanced laser technology also enables thin wafer dicing without cracking and chipping at throughputs higher than traditional dicing saws. It describes some innovative capabilities of laser machining through different materials including wafers with Low-k dielectric, stopping on a particular material, or modifying the electrical contact between material layers. These applications are emerging today in the packaging, testing, and bumping of wafers.
Laser drilling microvias in silicon, dielectrics and complex material stacks has higher throughput than conventional etch processes-a distinct advantage for 3D packages.
There are numerous emerging applications for direct machining of Aluminum, Copper, Nickel, Tungsten, Polyimide, Glass or BCB incorporating laser machining to achieve wafer level KGD testing. The opportunities in this area constitute are economically viable alternatives to the conventional packaging and testing.
Dick graduated from the Electronic Engineering degree program at the University of Minnesota with distinction and has since lived and worked in the US, Europe and SE Asia developing a broad career spanning many technologies including electronics, optics, vision systems, IC processing and device physics. Dick previously worked with Motorola, CDC, HP and most recently Agilent Technologies.
Substrate Mapping in Inkless Assembly PDF (.7MB)
Dave Huntley, Kinesys Software
The use of wafer maps generated at wafer test are now in widespread use for assembly of devices without ink. With the advent of strip test, final testing of devices in strip form, it is becoming necessary to use strip maps for use by singulation equipment. Consequently, there is a need to extend wafer mapping to include other substrates such as strips. There is a growing demand to mark devices with a unique tracking code or Device ID using the 2D matrix laser mark. Once a device can be uniquely identified in the field, it becomes valuable to be able to trace it to each substrate it belonged to during its manufacture and also what equipment those substrates were processed on. This presentation will cover the latest thinking on how to accomplish these advances as well as the standards that are in place and under development to facilitate their development and widespread use.
Session 4: KGD Test
High-Performance Wafer Testing Technology PDF (2.3MB)
Michinobu Tanioka, ASET
One of the most important technologies for achieving the ultrahigh-density three-dimensional stacked LSI is the high-performance wafer testing. The ultrafine pitch probe and the high-accuracy prober were developed to enable this technology. The material and structure of the probe tip were optimized based on preliminary experimental results using bare chip electrode samples. Excellent contactability was obtained by plating the probe surface with gold and when the electrodes were covered with electroplated gold bumps. As for the copper electrode, stable contact was obtained by changing the probe tip in order to break the oxide film on the electrode surface.
The signal transmission properties of the conventional micro probe structure were simulated, and a new probe card was proposed that improve the performance to 3GHz. Commercially available prober(±4.0µm) did not satisfy our target(±1.0µm). Therefore, the new high accuracy prober was developed that realized the probing accuracy of less than 1.0µm.
Consequently, the ultrafine pitch probing technology for application to 20µm pitch electrodes was established under constant probing conditions using the new probe and prober. In this presentation, the results of these technical studies are discussed.
Challenges of High Speed Probing PDF (1.1MB)
Thorsten Bucksch, Infineon Technologies
Known good die testing requires replacing the test of packaged components by an adequate test insertion on wafer level. Tests transferring from component to wafer tester without any changes delivers good results as long as the frequency range does not exceed 125MHz. State of the art memory devices require a higher test speed, taking into account DDR-II and DDR-III interface specifications. For high speed testing it is very important to know about the behaviour and the restrictions of existing technologies.
In contrast to component testing, the signals on the wafer prober cannot be accessed at any point within the system. Measuring introduces parasitics which influence and change the system behaviour. The model build of the individual system components and simulation-supported analysis activities allows faster development and deeper insights. Also, new implementations are necessary for the calibration methodology. When using Dual Transmission Line test setup, the standard reflective method cannot be used anymore. The Needle Auto Calibration system from TEL allows point-to-point measurements. Infineon Technologies, together with FormFactor, is targeting a 500MHz wafer level test. Based on existing results the definitions for a required test setup can be fixed. During the process, performance limiters have been identified and addressed in a second evaluation step.
Full Wafer Contact: From Dream to Reality PDF (2.0MB)
Steven Steps, Aehr Test Systems
For years it has been the dream of many back-end engineers to be able to test and burn-in an entire wafer all at once. This dream has been frustratingly slow in coming to reality.
This presentation discusses the potential cost benefits of full wafer contact for both test and burn-in applications. Some of the many advantages of full wafer contact for burn-in and test are discussed.
But this dream is not without some harsh realities. Some of the challenges that have delayed the implementation of this technology are discussed, along with some of the solutions.
The reality of the dream is then demonstrated with contact data showing the reliability and repeatability of full wafer contactors. A real customer application is demonstrated showing the flexibility of full wafer contact technology - a dream that has become a reality.
Innovative Solutions to Inspection Problems for Flip Chip and MEMS Manufacturing Processes PDF (2.7MB)
Tom Molamphy, Phoseon Technology
There are several inspection applications in the semiconductor fabrication and packaging arena that have solutions - and potential solutions - that can be based on the use of higher power monochromatic light sources as illumination for the inspection platform. Ultraviolet light can be used to great effect for inspection and measurement of many organic compounds including flux, conformal coatings and adhesives. Infra Red sources can be used effectively for inspection systems for Silicon applications such as MEMS seal inspection and potentially for under fill inspection. This presentation gives an overview of current work in this area and outlines some of the future potential.
Deep Submicron Test & Reliability Screens
Jody Van Horn, IBM
Abstract not available.
Session 5: Special Issues in Test
Dicing Frame Probe Application PDF (.7MB)
Kevin Chandler (presenter) & Tsutomu Yamaki, Tokyo Electron America
This presentation is a short review of the application of dicing frame probing relative to the KGD process followed by a discussion on how to achieve contact accuracy on after diced wafers. TEL will review alignment techniques for different applications, accuracy data relative to various alignment techniques and a review of concerns with Multi DUT testing as it relates to contact accuracy.
A Survey of KGD and WLP Test Handling Methods PDF (3.0MB)
Bob Fenton, Electroglas, Inc.
The current and increasing level of interest in Known Good Die (KGD) and Wafer Level Packaging (WLP) appears to be justified by the growth rate in shipments of these package types. Many analysts predict a high double to triple digit CAGR in shipments of KGD and WLP over the next several years based on increasing demand for System-In-Package (SIP) devices, handheld electronics products and personal communications gear. Traditional test methodology and handling/probing equipment have been adapted to these new test challenges, but may not be optimal in all applications for production testing of KGD and WLP. This presentation features several final manufacturing process flows for KGD and WLP that are in use or planned today. A representative case study of each process and a relative comparison between the methods used in terms of cost and throughput will be presented.
Retest/Reprogram of Die in Tape Test PDF (.8MB)
Ian Thomson, Advanced Integrated Materials
Whilst we always try to maintain the highest standards of products to our market, there are occasions when product is returned to us for retest or reprogramming. Retest or reprogramming has been a relatively easy task with component packages such as SOs, PLCCs, TSSOPs, QFPs etc whether returned in tubes, trays or carrier tapes. However, the industry should immediately consider how it can retest die or wafer level packages once they are off the wafer frame.
Micro-Tape is a punched carrier tape meeting EIA481-B standards and allows for test/reprogramming of the device in the tape once the cover tape is pulled back. After retesting/reprogramming, new cover tape is applied to secure the devices.
The presenter, Ian Thomson, will demonstrate how Micro-Tape can be used in a situation which calls for bare die and WLPs to be retested or reprogrammed.
Recent Advances in Low-Cost Multi-Gigahertz Testing PDF (2.7MB)
David Keezer, Georgia Institute of Technology
This presentation provides a summary of three research projects that are developing new low-cost techniques for testing devices with multiple channels of high-speed (>1 GHz) data. In the first project [1], we enhance existing ATE by adding multiplexing logic and high-speed sampling circuits. Modular circuits are added that support 12 high-speed differential signals with data rates as high as 2.5 Gbps. The system is expandable up to 12 modules, so that 144 differential pairs can be tested. The present system is stable up to 2.5 Gbps, with typical timing accuracy of +25ps and OTA under 100ps.
In the second project [2], an FPGA-based digital logic core (DLC) is used to produce moderate-speed (100-300 Mbps) data signals which create sub-picosecond bit periods, and multi-gigabit-per-second signals. These interface to optoelectronic components which modulate lasers of different wavelengths. The system is designed as a "test bed" for the evaluation of various OE and EO techniques. We have 5 channels for both transmitting and receiving, to support a 4-bit parallel data word and a "data valid" signaling bit. Minimum bit widths have been demonstrated at 300ps, with timing resolution of 10ps, and comparable timing accuracy. The objective is to provide low-latency transfer of small data packets within clusters of supercomputers.
In the third project [2], a similar DLC is combined with multiplexing and sampling PECL circuits to create a tester for checking high-speed data paths in a wafer-probing environment. The mini-tester produces a programmable data source up to 4.4 Gbps with 10ps timing resolution. A high-speed PECL sampling circuit is designed to capture the returned signal, also with 10ps resolution.
Session 6: Die Products Applications and Future Trends
Dimensional Stability of Optical Packages: a pre-competitive High Density Packaging User Group (HDPUG) PDF (.7MB)
Robert Sullivan, High Density Packaging User Group, Inc. Project
Like microelectronic packages, optical and opto-electronic packages are made with materials systems exhibiting thermal expansivity, thermal conductivity, glass transition temperature, creep and stress relaxation, and curing characteristics, which determine stability and reliability of either package/module type. Opto-electronic packaging exhibits extreme sensitivity to even minute changes in the system. A sub-micron scale misalignment of opto components is able to bring about significant losses. Organic adhesives can cause misalignment during the manufacturing process and lower yield and throughput. A pre-competitive multi-company project addressing these issues, sponsored by the High Density Packaging User Group (HDPUG) designed test vehicles (generic optical benches) to approximate real life situations. These test vehicles were modeled, both analytically and with finite element methodology. The modeling indicated measurable amounts of elastic deformation of the test vehicles upon thermal cycling.
Consequently, a follow-up project was initiated in 2003. Led by Dr. Ray Pearson of Lehigh University, this cooperative effort with HDPUG and the Center of Optical Technology (COT) involves the fabricating and testing of several structures for measurement of displacements and the refinement of the FEM Modeling.
Embedded WLP in PWB: The Next Stage of KGD Solutions
Takeshi Wakabayashi, Casio Computer Co., Ltd.
Recently we have seen widespread adoptions of WLP for portable devices. WLP has high electrical performance and high reliability. Also, we can use standard SMT process. As a next step, we are developing an embedded WLP in PWB as a next generation of System in Packaging technology. As one of KGD solutions, we can solve many problems to make a System in Package by using WLP instead of bare die.
Smart Sensor System for Mobile Medical Monitoring PDF (.5MB)
Kimberley Newman, University of Denver
A prototype of a wearable smart sensor system will be discussed. This system is designed to perform on-chip signal aquisition and transmission of data from a sensor to a remote monitoring system. The system described in this presentation consists of a temperature sensor that is interfaced to an FPGA through an external ADC. The FPGA system is then connected to a remote PC through an on-chip UART. The signals are monitored using Labview and alarm conditions are detected and reported on the monitor and transmitted to the remote unit for display. The monitor system is also capable of modifying the sampling rate of the remote system to obtain signals from 1 sample per second (1 Hz) to 1 sample per 60 seconds (0.0166 Hz). These frequencies may be adjusted in software if faster sampling time is required for specific applications.
Die Products in Automotive Applications PDF (1.0MB)
Greg May, Delphi Delco Electronics Systems
The automotive environment is one of the harshest environments for electronics. The operating temperature range is from _40ºC to +125ºC. This seems like an almost impossible environment for die products. At Delphi, we have been using bare die in the automotive environment for over 20 years. Leveraging this experience, we have moved from using die products on ceramic substrates to using flip chips on an organic substrate. This has allowed Delphi to build smaller, cheaper, and more reliable products to meet our customers needs. Making sure the flip chips meet automotive standards is a challenge. To meet this challenge, we must understand the technologies involved and evaluate all possible failure modes of the system, not just the flip chip device. With a constant focus on attention to detail, we are continuing to use die products in the ever-demanding automotive world.
Strategy for Supplying Bare Die to High Temperature Automotive Applications PDF (.6MB)
Peter Moberg, National Semiconductor Corporation
The operating temperature requirements for convential silicon are well defined for commercial, industrial, and military applications (TAMBIENT of +125C or less). As automotive engine compartments get hotter, a demand for high temperature versions (junction temperature, TJUNCTION > +125C) of standard ICs has been created. The "low end" of this high temperature range is a TJUNCTION of +150C to +200C with the "high end" being greater than +200C.
In general, a wide-bandgap IC possessing high thermal conductivity properties produces minimal leakage currents, resulting in improved electrical performance and better dissipation of heat. Presently, technologies being explored for use at +200C and above include SiC, GaN, GaAs and Silicon-On-Insultator (SOI).
For high temperature applications operating at the low end (+150C to +200C), bulk silicon semiconductors (bipolar and CMOS) may be suitable. Key to supplying high temperature versions of standard bipolar and CMOS semiconductors is understanding the possible device hazards that will affect device performance and reliability at these temperature extremes.
This presentation describes one strategy that was developed while evaluating the suitability of some standard analog devices. Included is an overview of the impact that a high junction temperature has on key electrical parameters and the long term effect it has on device reliability.
Flip Chip on Module Application PDF (.4MB)
Doug Bolen, Micron Technology, Inc.
The wireless handset, portable PC, and server/data storage markets are all driving a trend requiring more memory density in the same or decreased amount of space. This trend requires memory producers to develop and implement new component packaging technologies, such as wafer level chip scale packaging (WLCSP) to meet the application requirements. The materials used in the WLCSP process have been in development for many years and are not new to the IC packaging industry. Recent improvements in the characteristics of the polyamide materials used as a dielectric base lead to better electrical and mechanical performance. The redistribution layer (RDL) is an additional metal layer for electrical interconnect on which the connections from the original bond pads are redistributed over the surface of the die to new locations and ball pads. In this case, conductive bumps are placed on these ball pads. Micron anticipates a 256-megabit (Mb) double data rate(DDR) SDRAM in WLCSP technology to be available soon. Micron is also targeting emerging DRAM technologies, such as DDR2 SDRAM (double data rate, second generation) and beyond, with this emerging packaging technology.