Previous Workshops: 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007
10th Annual KGD Packaging and Test Workshop Summary
The 10th Annual KGD Packaging and Test Workshop was held in Napa, California on September 7 - 10, 2003. The workshop was attended by 127 persons representing 76 organizations worldwide. The workshop was again well attended by representatives from companies outside the USA with 25% of the attendees and 33% of the presentations coming from outside the USA.
Tutorials
The workshop began on Monday morning with 4 tutorials providing an in-depth view of certain aspects of particular die products technologies.
Introduction to Die Products This tutorial was developed in response to requests from previous years that we include an introductory session that would provide a background for attendees who were just getting started in the die business.
PWB Substrate Design Tutorial This tutorial was developed as an adjunct to a DPC project to develop guidelines for designers who are making the transition from a surface mount based application to a die products assembly.
Wafer Probe Tests and Stresses Used for Quality and Reliability Improvement This tutorial was based on a summary of the DPC Test Methods and Reliability Screens common experiment. The goal of the experiment was to reduce the requirement for burn-in.
Tutorial on Probe Technologies This tutorial was developed to give the attendees a better understanding of wafer probe technologies and methods in use for IC products today.
Back to topTechnical Program
The technical program consisting of 6 sessions of technical presentations was held over the next two days.
Session One offered a detailed look at the business and market conditions for die products. The keynote address by Dr. Bill Bottoms, CEO of Third Millennium Test Solutions, set the tone for the workshop. Dr. Bottoms, as a key contributor to the International Technology Roadmap for Semiconductors, shared insights into the direction of the IC industry in general, and pointed out the opportunities for the die products industry. Other speakers in Session One emphasized the tremendous growth being experienced by the SiP and 3-D packaging technologies, especially in the mobile product market. Presentations focused on market analysis for these novel packaging technologies, packaging company roadmaps for multiple chip packages, and discussed end applications that incorporate die products. Session One concluded with a panel discussion addressing the expectations for the next 10 years regarding die products. The speakers in Session One plus a representative of Micron and an attendee from a China company offered their reflections on where the industry has been, where it is going and the challenges that must be met.
Session Two and Session Three were offered in parallel with Sessions Four and Session five, as the first two focused on packaging and the latter two on test.
Session Two focused on multi-die packaging technologies and emphasized that the infrastructure to support the die products business was now in place worldwide. New stacked package formats, reliability studies, die and substrate requirements, and qualification test plans were discussed through six presentations by industry practitioners. It was observed that stacked-die and stacked-package packages were both being developed now, and each served its own assembly/cost paradigm, with tradeoffs being made on issues such as cost of test for die vs. package. High density substrates to support high frequency electronics is a focus of the industry as die products move into the mainstream for mobile products. Presentations specified the requirements for realizing the high density demands of die products in substrate technology in terms of line/space widths, number of layers and via formation. Session Two also included detailed discussions of bumping for LCD applications, including Chip on Glass and Chip on Flex, as well as pre-applies underfill technology improvements.
Session Three was the second session of the packaging track and the presentations continued the same types of discussions as Session Two. Included was an overview of bonding processes for flip chip applications, including an application of plastic-cored solder balls that improve standoff height and can improve reliability without underfill. This session also included a discussion of inkless mapping of test data onto devices for enhanced assembly processes.
Session Four began the test track of the workshop. Following the interest in high performance probing, there were several presentations in this session detailing the latest in probing technology and methods. Probing technology practical for ultra fine pitch (<20µm), array pad geometries and high speed functionality were discussed. Presentations specific probe needle materials, geometries and contact properties for advanced IC wafer test regimes. Also included were comparisons of wafer to package level test effectiveness. Test process flows were presented that aim to achieve the same level of testing at wafer probe as in the final package. The session also included a discussion of novel inspection equipment being developed that uses high intensity monochromatic light that enables cost effective, high performance die products inspection solutions.
Session Five continued the test track. The emphasis on wafer testing continued in this session, with technologies presented that allows testing of singulated die on wafer film frames. This allows testing later in the back end process, i.e., after wafer sawing. Algorithms have been developed that support multi die testing of singulated die on film frame, which is seen to be an advantage for both bare die and wafer level package die, especially those that are ultra thin. Also included in this session was a discussion of testing of die while in the packing medium, allowing final testing at the very end of the backend process.
Session Six focused on applications and future trends. The session included a discussion of optoelectronic packaging, including material properties and dimensional stability of opto packages. Physical parameters such as CTE, thermal conductivity, Tg, creep and stress relaxation and curing characteristics were discussed as being important parameters for future packaging of optoelectronics modules. Also included in Session Six was a discussion of a novel chip in substrate embedded technology. There were two presentations that focused on automotive use of die products, which is seen as a emerging market for these applications. This session also included a discussion of the IC fabricators view of the opportunities and hurdles to producing quality die products in a cost effective manner.
Back to topExhibition
The workshop also included an exhibition of die products equipment, material and supplies from 24 companies. Half of the exhibitors at the 2003 workshop were participating as an exhibitor for the first time. Several exhibitors were recognized for continued support of the workshop throughout the last decade. KGD Industry Leadership Awards were presented to the following exhibitors: 3M, Aehr Test Systems, Chip Supply, Inc., Eltek Semiconductors, Gel-Pak, National Semiconductor Corporation, and Mintech Semiconductors. A reception in the exhibits area on Monday evening facilitated networking within a dynamic social atmosphere.