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2004 Workshop Technical Program
Pre-Workshop Tutorials
101: Introduction to Die Products
Larry Gilg, Die Products Consortium
102: Wafer Thinning & Handling of Thinned Wafers and Die
Werner Kroeninger, Infineon Technologies AG
103: Wafer Level Packaging
Eric Beyne, IMEC
Session 1: Business Issues & Market Trends
Keynote Presentation PDF (3.8MB)
Carlo Cognetti, STMicroelectronics
Trends in 3D Packaging PDF (3.8MB)
E. Jan Vardaman, TechSearch International
Three-dimensional (3-D) packaging has been used in production for the last 20 years. Many of the early applications were high-end computing, military, and aerospace applications. The growth in the market is driven by the rapid expansion of stacked die and stacked packages in portable electronics. Just as the applications of the past, today's products require extremely small formfactors. Almost every mobile phone and digital camera contains at least one stacked die CSP. Stacked die packages are also found in personal digital assistants (PDAs). While much of the volume has been in the two die stacked package, an increasing number of stacked die packages with three, four, or five die are shipping. Examples of eight die packages can be found in limited production. The majority of packages shipping today are wire bonded, but flip chip is on the roadmaps of both semiconductor makers and IC package contract assembly houses. While most of the stacked die packages shipped historically are memory (flash and SRAM), packages containing logic devices are also increasingly moving into production. Among the advantages of stacked solutions include smaller form factor, fast turn-time, and low NRE costs (compared to a single die design). The key challenges of stacked die products include both logistical and engineering issues. Issues related to die include wafer thinning, bare die, known good die (KGD), die attach and wire bond, and thermal dissipation.
SiP Technology Development in Japan PDF (1.4MB)
T. Onishi, Grand Joint Technology
This presentation will cover key SiP packaging technologies. Topics will include thin wafer back grinding, stress relief, dicing, pick-up, and fine pitch.
Test Flows for Consumer SiP PDF (.1MB)
Peter O'Neill, Agilent Technologies, Inc.
As cost-sensitive consumer products drive the growth of SiP, the concept of "as close to perfect as practicable" known-good die (KGD) of the earlier high reliability military/aerospace/ automotive MCMs must be replaced by the more economical and flexible concept of knownquality die (KQD). With KQD the system integrator can determine what further testing must be done to achieve his finite quality target and trade that for the cost of testing and scrapped material and effort. A variety of test techniques can be used to provide die of higher known quality depending on the function of the die and the quality target: moving package test directly to probe; generating, observing, or transforming difficult signals with DfT or BIST; or indirect testing with DBT or model-based techniques. At package, since the dice have already been tested internally, interconnect can be tested by boundary scan and tolerance accumulation handled by simulation.
KGD DRAMS - Truth vs. Fiction PDF (.7MB)
Lee Nevill, Micron
From a DRAM perspective, there are a multitude of factors requiring careful explanation and consideration on the consumer's behalf. Consumers often make assumptions and inferences which are not entirely truthful in the context of quality, reliability, and cost of Known Good Die. Often, it is found that the beliefs are based on experience that has been gained from logic testing paradigms. Consider the following commonly expressed perceptions:
- Since no package is required, Known Good Die should be cheaper than a packaged part
- 2) DRAMs are digital and once tested at wafer level, should never need tested again
- 3) Quality and reliability of KGD needs to be equivalent to that of a packaged part
- 4) Wafer level burn is commonplace in the industry today
In this presentation, each of these statements will be carefully examined. It is not the intent of this presentation to dismiss these statements as totally unrealistic or totally fictional, but merely an attempt to provide insight to the challenges in supporting the statements as 100% truth.
A Novel Technology Enabling DRAM Die Stacking in SiP PDF (.7MB)
Fan Ho, Inapac Technologies, Inc.
Inapac Technology's DRAM die products have been qualified to the most demanding industry standards without requiring oven based burn-in. This is a worldwide industry first and a critical enabling technology to allow the integration of high density memories into Systems in a Package (SiP).
The presentation will cover the physical principles behind this new methodology, then it will describe the on-chip test circuitry needed to implement Inapac's Voltage Induced Burn-in Emulation technology (VIBE). It will also cover the specific test challenges both at the wafer level and following packaging into the SiP, at the final test level.
The end results of extensive correlation studies between traditional burn-in and Inapac's VIBE will also be presented. These studies have been conducted over a variety of DRAM manufacturing processes including both stack and trench technologies.
Finally, some test results will be presented showing the resulting test efficiency and final product quality level.
Session 2: SiP-Enabling Technologies
Realizing Low Cost and High Reliability in CSP Packages with Surface Treatment and
Material Technology PDF (1.8MB)
Ryota Furukawa, Panasonic Factory Automation Company
In many cases CSP package production has been done by wire bonding methods because of its low cost and actual results. In this case the wire bonding electrode and solder ball attach electrode are made by the same plating process.
As for wire bonding electrode, the thinner the thickness becomes, the worse the bonding quality will be. Therefore, considering the wire bonding quality we usually have to use thick Au plating. On the other hand, regarding the solder ball attach electrode, Au plating thickness should be as thin as possible. Moreover, if you use electroless Au plating to get high density wiring, you have to use Nickel-Phosphorus plating as the barrier layer underneath the Au plating. In this case a phosphorus rich layer is made at the interface of solder ball bonding phase and could be detrimental to solder ball attach reliability. This has been a big problem that should be solved according to shrinking the solder ball diameter.
Thus there is a discrepancy in optimized Au plating thickness between the wire bonding and solder ball attach electrode. In order to overcome this contradiction, we have developed plasma cleaning process that can realize excellent wire bonding quality even with the thin Au plating.
Plasma Stress Relief Technology for Wafer Thinning Process PDF (.9MB)
Kiyoshi Arita, Panasonic Factory Solutions Co., Ltd.
AVX Corporation, a Kyocera Group Company, is a leading worldwide manufacturer and supplier of electronic components. The company needed a high-volume solution for extracting bare die resistors from wafers to perform inspection, testing, marking, and packaging for use in highend medical products.
Exatron, which manufactures automated handling, testing, programming, and marking equipment, teamed with Hover-Davis, the inventors of the world's first direct die feeding system. Their solution for AVX integrates production-level die handling and testing for high-speed, high-quality results.
The presentation, which will incorporate testimonial input from AVX, will review how the problem was assessed and the resulting requirements. It will describe the basis for the eventual solution, offer performance metrics, summarize the benefit of the solution, and describe its application to KGD manufacturing workflows.
Integrating Die into a High-Volume Manufacturing Process PDF (1.7MB)
Corey Davis, Hover-Davis, Inc.
In today's world, inspecting die can help protect your number one concern: yield. Die inspection allows us to identify defects, but using detection to make a decision is necessary to help your bottom line. Packaging known good die is important to all involved in this industry and everyone can benefit from useful inspection information. Manufacturers can increase yields, good die can be packaged, and ultimately consumers can reliably have quality products.
Transforming defect data into information that can be analyzed allows you to make effective decisions. MA/COM efficiently and effectively takes their defect information to make decisions that increase yields, cut costs, and use information throughout the manufacturing and packaging process. MA/ COM has used inspection results to improve processes in the fab, report die level information to the post fab, and determine which die to package and ship. MA/COM has gone from detection to decision and yielded great results.
Inspection - Detection to Decision PDF (1.7MB)
Stephen Potter MA/COM & Jolene Banttari, August Technology
This presentation describes plasma stress relief technology as a method for good reliability of wafer thinning process. Mechanical damage layer including micro crack occurs in the back side of silicon wafer during grinding process. It becomes a critical factor of wafer crack or warp. Therefore, the stress relief process removing the mechanical damage layer has become increasingly significant technology. We report that a new dry, clean and non-load stress relief process using plasma etching technology is a very attractive method for wafer thinning and can be applied to a DBG (dicing before grinding) process for smart card packaging.
Semiconductor Wafer Thinning Technology PDF (1.6MB)
Mark Brown, DISCO Hi-Tec America, Inc.
Stress relief technology is essential for the wafer thinning process, especially when it is thinned down to 100 microns or more. It is selected depending on the type of device. Examples of applicable technologies include dry polishing for stacked package device, a combination of DBG (Dicing before grinding) and plasma etching for device used IC cards, and spin etching for discrete devices.
Processing the silicon wafer is not the only technology involved in the wafer thinning process. Various other technologies and knowhow are also part of this process: the selection of the surface protection tape, DAF (Die attach file) lamination, and tape removal from thinned wafer (which is the most difficult process). DISCO has succeeded in producing a machine that integrates such technology.
Package-in-Package: A 3-D Stacked Package Module PDF (1.9MB)
Marcos Karnezos, ChipPAC Inc.
Stacking of tested good packages instead of stacking die in a CSP is desirable for many new wireless applications that require integration of a complex ASIC, analog and memories like Flash and high speed DRAM. In this novel Package-in-Package (PiP) module, two or more tested good packages are stacked and interconnected using wire bonding, and are molded much like the die in a conventional, JEDEC standard stacked-die CSP. The same basic packaging assembly, test and supply infrastructure is used to produce a low cost package with minimal risk and very short time to market. Results show that PiP meets all the package and board level reliability requirements including lead free and green conditions without any compromise compared to the standard one-die CSPs. The wireless application and future variants stacking a mix of die, packages and a mix of technologies including wire bonding, flip chip, shielding and passives will be described.
SiP Experience and Future Directions PDF (1.3MB)
Ralf Plieninger, Infineon Technologies AG
As an IDM with a broad product spectrum in wireless and wireline communication, automotive and industrial, security and memories, Infineon Technologies sees applications for KGD and SiPs in many of its application areas, driven by the well known advantages in cost, size, time-to-market and performance. The presentation will show examples form several application areas and highlight the common learnings for future development.
Session 3: KGD Test & System Verification
Developments in RF Test and Map Management for KGD PDF (1.5MB)
Chris Jones, Tyco Electronics M/A-COM
M/A-COM has produced RF and microwave Known Good Devices (KGD) for over 20 years. During this time we became proficient with wafer level testing to 26GHz and the delivery of KGD for low volume applications.
Over the last two years M/A-COM has retooled its processes to support the high volume KGD needs of cell phone module manufacturers. The primary product family is low distortion multiport switches operating at or less than 3GHz.
This presentation will discuss the use of Cascade Microtech's Pyramid Probe in terms of design attributes, calibration approach, repeatability, cleaning cycle and life cycle. Following will be a summary of test improvements including setup qualification, adaptive probe cleaning, predicitve sampling and restart / retest functionality. Finally a wafer map management tool will be reviewed which supplies maps to processes, performs error checking of process outputs, merges results and incorporates logic to prevent unevaluated wafers from being delivered.
3D SoC Slashes Test Cost PDF (MB)
Jeff Lick, Ziptronix, Inc.
A key problem for conventional SoC solutions is test. With conventional SoC, there is no opportunity to use KGD selection to improve yield. SiP can use KGD information to enhance yield, but SiP approaches are plagued by other problems that impact packaging cost and reliability, particularly with regard to thermal management.
We will present a new SoC approach. 3D SoC enables KGD selection in the creation of a single chip SoC. This significantly enhances yield and reduces the cost of test. At the same time the resulting single chip solution greatly reduces the cost and complexity of packaging and assembly operations and can be used in high performance applications where power dissipation and interdie propagation delays prevent the application of SiP solutions. The 3D SoC option combines the key strengths of SoC and SiP while at the same time eliminates the weaknesses that have limited their use in today's markets.
Test Support Modules with Jitter Injection at 5 Gbps PDF (1.6MB)
David Keezer, Georgia Institute of Technology
Last year at the KGD Workshop we introduced a method for testing at 2.5 Gbps by multiplexing 1 Gbps channels on a production test system. This year we present a variety of transmitter and receiver modules that further extend the test rate to 5 Gbps, with additional functionality and improvement in timing accuracy (below 50ps).
The approach uses the modules in an active loadboard configuration. The loadboard supports as many as 12 of the modules, with each module handling between 2 and 24 high-speed signals. So far we have developed 12 different types of modules, so the specific combination can be tailored to the DUT test requirements. The active loadboard is controlled from a production tester (Agilent 93000-P1000) with about 900 channels and a maximum frequency of 1 GHz.
Another test function that is needed for many high-speed devices, that is not typically available on ATE is that of jitter injection (for measurement of jitter tolerance). With this in mind, we have included jitter-injection circuits in several of the higher-speed modules.
The modules developed so far are targeting general-purpose digital logic devices. However, we are also developing specialized modules that provide test functions unique to particular device types. The modular active loadboard approach facilitates the quick introduction of such new test features.
TDR Measurement Techniques for Package Variations PDF (.1MB)
Justin Davis, Mississippi State University
This presentation provides a summary and status of on-going research projects that are developing methods to include the package lead, wire bonding, and MCM carrier in time-domain reflectometry (TDR) measurements. The method integrates the test structures onto the wafer to allow for the variations present in different devicesunder-test. With the test structures present onchip, the test can be performed on all I/O pins without external equipment. This minimizes test time and aids repeatability.
The specific application will focus on programmable chips so the test structures can be instantiated after production. Once the test is complete, the functional circuitry can replace the test structures which minimizes the amount of logic required. This will allow for variations in the manufacturing process. This method also applies to fixed silicon, system-on-chip (SOC), and system-on-package (SOP) implementations by enhancing the test structures already in place (JTAG) to include TDR measurements. TDR was chosen for its diagnostic information, but eventually all signal quality tests should be included on-chip such as bit-error rate and jitter tests.
Selective Burn-in, ASAP PDF (.1MB)
Jerry Secrest, Secrest Research
This paper analyses a proposed approach to reducing die burn-in to a minimum, as soon as possible. The approach is to use available equipment and data to sort the die product into "suspect" and "clean" material. Using fab, E-test, Wafer history, Sort data, and Short-term burn-in data, sorting accuracy maybe improved to the point where some material does not require burnin. The objective is to keep die in wafer form for burn-in or to defer burn-in to after the die is hooked up at board level.
Data from short-term burn-in in wafer form is used to find the root cause of reliability failures in fab. Wafer form data simplifies the tracing of the root cause. The cause has to be "repaired" such that future material has improved reliability.
There is one condition where burn-in is effective. It is the burn-in failure rate is high enough for the burn-in to be cost effective but lower than the level where the product has latent failures in the population. The proposed approach is used to sort die in wafer form into a population that has low failure rate and into a population that needs burnin.
Driving Down the Cost of Burned-in KGD PDF (.5MB)
Steve Steps, Aehr Test Systems
This presentation will focus on innovations to temporary, bare-die carriers, which make it more cost-effective for use in both flip-chip and WLP applications. A cost model comparing burn-in with this new ("DiePak") carrier, wafer-level burn-in, and burn-in using micro BGA sockets for WLP devices will be reviewed. Compared to the micro BGA sockets and to previous versions of the temporary, bare-die carrier, the new temporary, bare-die carrier will be shown to offer a lower-cost burn-in solution, saving capital, labor and consumables. This new solution is already in production for applications for flip-chip and WLP burn-in. Demand for burn-in of flip-chip and WLP devices is increasing as these packaging technologies are starting to be used in mobile electronics for ICs that require burn-in, such as DRAMs and micro-controllers.
A KGD Enabler: Full Wafer Contact Technology PDF (1.7MB)
John Pitts, Freescale Semiconductor, Inc.
Freescale Semiconductor has developed and qualified a full wafer contact technology to enable Known Good Die (KGD) microcontrollers for the automotive industry. Today, there are only a few processes that can deliver true KGD. Statistical good die selection, test methods like HVST and Iddq, burn-in via individual die carriers, and sacrificial metal wafer level burn-in are commonly used in the industry today. These processes are nearing the limits of their technology, screening effectiveness, and cost effectiveness. Thus, the next generation process of directly contacting the full wafer was developed to overcome existing technologies' limitations. This paper compares these various processes, their strengths/weaknesses, and defines the roadmap to achieving KGD.
Session 4: Applications & Future Trends
Die Optimization for COF assembly PDF (2.0MB)
Hamit Duran, Philips Semiconductors
Philips Semiconductors Zurich has a lot of experience with the development of display driver ICs, which are used to drive LCD displays in mobile phones, PDA's, laptop and PC monitors, and flat TV sets. Most of the ICs are delivered as naked dies (KGD) or assembled in a Tape-Carrier- Package (TCP) to the customer. However, chipon-foil (COF) is getting more and more popular due to its fine-pitch and low cost potential.
Philips discovered that optimal die pad and bump design is essential when switching from KGD and TCP to COF. It turned out, that special layout rules must be followed in order to achieve good yield and reliable COF production.
This presentation will outline the most important aspects that must be kept in mind when designing display driver ICs. Issues like bump structure and location as well as stress relief structures will be addressed, and guidelines will be presented. For a better understanding of the effects, a thermomechanical simulation model of the COF assembly process was developed. Simulation results will be presented and the results compared to actual data obtained from real production.
System In A Package (SiP) Test: An Old Dog - New Tricks . or is it? PDF (.6MB)
Jody Van Horn, IBM
Multi-Chip Modules have been a cornerstone of IBM 's Server business for decades - and remain so today - however with the kaleidoscope of function and technologies demanded by the cell phone / consumer space, the world has changed. Or has it? Is this new SiP acronymn just a low cost application of MCM principles (old tricks)? Or is SiP another name for the old "cost is no object" MCM dog that must learn new tricks to be viable in this "cost is King" market?
This discussion will attempt to determine what test principles still apply, and from those begin to show what puzzle pieces we have , what are being addressed, and what new work is necessary to provide solutions to this market.
Qualification of Flip Chips for Automotive Applications PDF (3.2MB)
Greg May, Delphi Electronics & Safety
We use flip chips in our products for a variety of reasons. Smaller size, excellent heat removal, and lower cost. The handling of flip chips has presented many challenges including qualification. Traditionally, Delphi and other automotive companies have used packaged ICs and the reliability testing is rather standardized. With an unpackaged part like a flip chip, the usual stress tests present new challenges. In addition, the stress tests that apply are different due to the unpackaged nature of the component.
My paper will present how Delphi approaches the qualification of flip chips for automotive use. Our qualification is performed to the Automotive Electronics Council's AEC-Q100 testing procedure. At Delphi, we are using test coupons for validation of the components run through environmental testing. This provides a good simulation of the device's use in the actual system without involving all of the support components.
I will also discuss why each of the tests is applicable to the flip chip qualification and share some of the failure mechanisms that have been found during qualification.
Integrating MEMS with Standard CMOS Using Low Temperature Poly-SiGe Technology PDF (1.3MB)
Philip Pieters, IMEC
New portable consumer electronics are requiring that power consumption be reduced. MEMS components may add unique functionality to such portable electronic devices as well as miniaturization and low power consumption. Post-processing MEMS devices directly above their CMOS control circuitry allows a significant reduction in size of the total MEMS function and provides a very short low loss interconnection.
Post-processing of MEMS directly above CMOS is not possible by using standard poly-Si micromachining technologies, as temperatures of 800°C and more. These high temperature steps kill the CMOS devices below. When using poly-SiGe instead of poly-Si, processing temperatures may drop to 450°C and below., which is compatible with CMOS ICs.
This technology opens a lot of new perspectives towards the integration of existing MEMS components and in development of new miniature microsystem functions and 0-level MEMS encapsulation. The post-processing approach allows the optimization of the MEMS device and the CMOS circuitry independently, yielding optimum system solutions.
WFP (Wafer-level Fabricated Package) for High-Performance DDR2 SDRAM and Memory
Module PDF (2.3MB)
Gusung Kim, Samsung Electronics Co., Inc.
Recently, Samsung announced the industry's first wafer level package (WLP) for high-performance 512Megabit (Mb) DDR2 SDRAMs. This is truly focused on optimal package solution for mobile environments and high-density memory modules.
The new package technology, WLP, is originated from the wafer level process. Two patterned interlayer dielectrics (ILD), with insulating characteristics, and a metal layer replaces the conventional package substrate. Ball grids give the appearance of a chip scale package (CSP) that is scaled down to the actual die size. The product, WFP (Wafer-level Fabricated Package), supports the JEDEC specifications for DDR2 CSP. Without further modification the DDR2 WFP can easily replace the CSP form allowing system designers to facilitate the introduction of WLP for KGD level DDR2 SDRAM applications.
This presentation describes one strategy that was developed while evaluating WLP for DRAM applications. Included is an overview of the impact that trade-off between the business and technology factors are considerable.
SEMI NanoForum Preview PDF (.3MB)
Ellery Buchanan, Ultratech, Inc.
Session 5: WLCSP Technologies
The APiA- An Industry Resource PDF (.8MB)
Ellery Buchanan, Ultratech, Inc.
The Advanced Packaging and Interconnect Alliance (APiA) is an unprecedented association of leading equipment, process technology and process material companies representing the foremost authorities on emerging packaging and interconnect technologies. The APiA is focused on accelerating the development and implementation of commercially viable, comprehensive and riskfree packaging solutions that address the escalating manufacturing and performance challenges of leading-edge chipmakers worldwide. As such, the Alliance concentrates on enhancing the productivity of the equipment and process solutions critical for advanced packaging and interconnect processes.
This presentation will highlight current activities of APiA, and discuss its commitment to improved cost of ownership through advanced technologies. Examples of the projects that are being undertaken to accelerate technology development will also be discussed. Attendees will be shown how to participate in the various APiA programs and the expanded continuing education programs of APiA will be described.
Metal Deposition by PVD for UBM/ RDL and Backside of Thin Wafers PDF (.8MB)
Hans Auer, Unaxis Semiconductors
This presentation gives an overview over wafer level metallization applications by PVD (sputtering) in the advanced packaging arena, in detail covering under bump metallization (UBM), redistribution line metallization (RDL), passive integration and backside metallization on typically thinned wafers. While the metallization for UBM and RDL on the frontside of the wafers has been quite prominent for some time for high performance devices as well as WLCSP, the backside metallization has recently become a hot topic for power management improvement to allow attachment of the heat sink by solder.
All the metal systems being applied either on frontside (UBM, RDL) or backside of the wafer serve as adhesion layer, diffusion barrier, and wetable base for the solder materials. In the case of fine pitch UBM or RDL as well as planar coils (integrated passives) the sputtered layers are used as a plating base and consecutively additional metal is plated followed by solder.
Popular metal systems for the different applications along with technological implications will be discussed. Additionally, technological requirements of the process tools, process control knobs to achieve desired film properties including pre- and post treatment as well as optimized configurations of sputter systems for small and high volume production will be presented along with associated cost of ownership data.
Demands on Coat/Bake Equipment Flexibility in Wafer Bumping and Advanced Packaging PDF (.2MB)
Uwe Dietze, STEAG HamaTech
Greater flexibility and expandability are required for processing the wide assortment of photolithographic materials on a variety of substrate sizes and conditions. A modular equipment approach decreases cost of ownership by addressing key wafer handling and process elements.
High viscosity resists and other photo definable materials require different processing conditions from the low viscosity materials used in standard integrated circuits. Coating systems must handle chemistries used in positive and negative tone coatings, maximize coating uniformities, and control solvent retention in the film to optimize the EBR process. Hot plate baking is the most widely used method for removing solvents from resist coatings; however, special considerations to time and temperature need to be realized. Depending upon the material and film thickness, time also needs to be allotted for film hydration prior to exposure. The image development time and method are also very significant in achieving optimum profiles. This presentation will address the importance of equipment flexibility to meet the current and future demands for thick resist materials used in the advanced packaging market.
Exposure PDF (MB)
Steven Kay, Ultratech, Inc.
Electrolytic Plating for WLP PDF (2.0MB)
Dan Ramirez, EBARA Corporation
As wafer level packaging (WLP) requirements for devices becomes increasingly complex due to increased chip circuit density, operating speed, and performance, electrolytic plating is necessary to produce a reliable and cost effective fine pitch bump process. The WLP flow is reviewed with a focus on the plating applications, associated issues and proven technology solutions.
Inspection - A Systems Approach PDF (1.5MB)
Rajiv Roy, August Technology
Inspection is covered as a process all the way from detection of defects through refinement of defects and then finally making a decision based on the defects. A systems approach to laying out the architecture is presented.
Emerging challenges in inspection such as low-K and all-surface inspection is also covered. The August architecture for a scalable and modular architecture to meet these challenges is presented.
General Processing Considerations for Thick Film Resists used for Wafer Level Chip
Scale Packaging PDF (3.6MB)
Mark Neisser, AZ Electronic Materials