The 11th Annual KGD Packaging and Test Workshop was held at the Embassy Suites Hotel in Napa, California on September 13 - 15, 2004. Attendance was 25% greater than the previous year, with 157 persons from 97 different organizations participating. The quality of the technical program was very good, the social program allowed time for networking and the feedback was positive.

Die products are increasingly the solution of choice within the mobile and consumer electronics markets, and the recovery for this segment of the market has been very robust. In answer to the rebound in demand for advanced packaging this year, the theme of the 2004 KGD Workshop was "Focus on Final Manufacturing", with tutorials and technical presentations spotlighting technologies emerging today to support the market demands for stacked packages, wafer level packages, bumped and bare die.

Program

The program this year was similar to past years. The technical sessions began at noon on Monday, September 13 and were preceded that morning by three mini-tutorials.

Tutorials

The tutorials included:

• An overview of die products
• Wafer thinning and handling of thinned wafers
• Wafer level CSP

The overview of die products is a version of a tutorial that is offered each year to introduce newcomers to the terminology and issues related to procurement and use of die products. The information is updated annually.

The wafer thinning tutorial was a very technical overview of the issues related with thinning wafers and handling of thinned wafers and die. The presenter, Werner Kröninger of Infineon brought samples to pass throughout the audience, which helped illustrate his points very well.

The Wafer Level CSP tutorial presenter was Eric Beyne of IMEC, who has done extensive research on all aspects of wlcsp. His tutorial was wide ranging, from technical approaches to economic analysis. This tutorial served as a good introduction to the wafer level csp session on Wednesday morning of the workshop.

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Session 1: Business issues and worldwide markets

The technical sessions began Monday at noon, with opening remarks by Jeff O'Dell, CEO of August Technology and general chair of the 2004 Workshop. Session 1 kicked off with the keynote address delivered by Dr. Carlo Cognetti, vice president of new package development for ST Microelectronics. Dr. Cognetti traced the requirements of system integration for packaging innovations and the impact on the microelectronics value chain. Dr. Cognetti concluded that System in Package is the reality for the industry today, either as an alternative or complementary to SoC and allows much more integration than Moore's law predicts.

The highlight presentation of Session 1, and perhaps of the workshop, was Lee Nevil's presentation on KGD DRAMS - Truth vs. Fiction. Mr. Nevil explained why KGD DRAMS will cost more than the packaged equivalent, and he questioned the requirement for the KGD product to meet the stringent quality and reliability targets of packaged devices.   He also disclosed "the dirty little secret" of DRAM, that temperature excursions during the assembly process can shift certain parameters out of spec, causing the device to fail in the system. Therefore, testing after assembly is crucial, and in the die products world, that testing burden will fall on the customer - or a 3rd party assembly manufacturer. In summary, Mr. Nevil emphasized that since it is expensive to test DRAMs in wafer form, the quality and reliability requirements need to be realistic for the application. Additionally, the die products supplier must support customers by offering DRAM test capability.

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Session 2: SiP-enabling Technologies

Session 2 offered attendees an in-depth look at the technologies that are being developed for production of state-of-the-art systems-in-package, today's first choice for multi-chip packaging. Two of the presentations provided more detail on the wafer thinning issue, highlighting specific areas that were introduced in the morning tutorial.

In a new twist on the stacked die package phenomenon, Marcos Karnezos described STATSChiPPac's technology development to stack wafer level csp packages vertically, creating a "package on package" product. This allows the customer to sidestep the tricky sourcing, test and reliability issues with KGD processes. Dr. Karnezos emphasized that the process utilized standard assembly processes, materials and components, resulting in high final test yields.

In the wrap-up presentation of the session. Ralf Plieninger discussed Infineon's long track record for SiPs in automotive and industrial applications of more than 10 years with more than 50 different products. Dr. Plieninger reviewed the applications for SiP at Infineon, and gave a detailed overview of the benefits and challenges of the SiP approach to implementation. Dr. Plieninger concluded the presentation with key findings for future developments.

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Session 3: KGD Test and System Verification

This session was in parallel with Session 2, as the topics were different enough that attendees would prefer to attend the session with presentation in their area of expertise. The first presentation of the session set the tone for an excellent line-up of presentations. Chris Jones of M/A-Com detailed how his company moved into a high volume producer of high quality, low distortion multi-port switches operation at 3GHz for cellular handset applications. Mr. Jones discussed the improvements in test, qualifications, probing and predictive sampling as well as wafer map management that were required to make the adjustment to a high volume manufacturing environment.

With wafer level burn-in technologies continuing to attract much industry attention, the second half of Session 2  was devoted to this topic. John Pitts of Freescale Semiconductor described the full wafer contact systems developed at Freescale, and compared that to the sacrificial metal wafer level burn-in and die level burn-in using carriers. Mr. Pitts concluded that none of the methods of burn-in for die products was optimal, but that that direct contact wafer level burn-in had the potential to meet the pitch requirements of the future.

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Session 4: Die Products Applications and Future Trends

This session explored some of the applications problems and offered a glimpse into the future of the technologies that will be needed as the customers continue to demand smaller form factor electronic systems for lower and lower price. Jody Van Horn compared the requirements for test and reliability screening of the new SiP products with their former incarnation as multi-chip modules (MCMs). Jody aimed some observations to the IC supplier who needs to take responsibility for providing quality for the SiP, and also at the system integrator who will be responsibility for testing the completed module. The testing problems for true SiP (heterogeneous devices, i.e., memory, logic, analog, etc) are formidable, not to mention the failure analysis and yield learning complexities for the factory.

Gusung Kim of Samsung unveiled a wafer-level fabricated Ppckage for high-performance DDR2 SDRAM and Memory Modules. The technical drivers for the development were lower cost than the current package, high speed design availability, thermal solution and high reliability. Mr. Kim outlined the structure of the package, the process flow and the cost simulation. The high performance solution is a result of market demand.

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Session 5: Wafer Level Packaging (presented by APIA)

The Advanced Packaging and Interconnect Alliance (APiA) is an association of equipment, process and materials companies who provide solutions for advanced packaging and interconnect technologies. The APiA is focused on accelerating the development and implementation of commercially viable, comprehensive and risk-free packaging solutions to address manufacturing and performance challenges of chipmakers worldwide. As such, the APiA concentrates on enhancing the productivity of the equipment and process solutions critical for advanced packaging and interconnect processes, as well as developing guidelines and standards to enable easy adoption of these sophisticated solutions.

The APIA presented 5 presentations on all aspects of wafer level packaging from deposition, coating and baking, plating and inspection. The Monday morning tutorial was an excellent introduction to the more detailed presentations made by practitioners in this session.

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