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A 5Gbps Stand-Alone Miniature Wafer-Level Tester
Ashraf Majid, Georgia Institute of Technology
New packaging techniques such as system on package (SOP) have allowed integrated devices to contain multiple components such digital, analog, RF, MEMS, etc. The complexity of testing such devices has increased dramatically and the cost of testing has become a large portion of manufacturing costs.
This presentation describes an economical approach to high-speed testing of high-density wafer level packaged logic devices. The solution assumes that the devices to be tested have built-in self test features, thereby reducing the complexity of functional testing required and the need for expensive automated test equipment (ATE). A stand alone miniature tester has been developed which can be connected to the top of a wafer probe card to test multiple devices at once.
This allows the mini-tester to test devices during separate stages of fabrication. For instance, after the digital, RF, MEMS, etc. components have been fabricated, thus reducing test complexity.
Multiple high-speed (2-5 Gbps) signals have been demonstrated. Because the tester uses off-the-shelf components a small amount of timing uncertainty is introduced to the system, therefore methods of timing calibration are also discussed.
Ashraf Majid received the B.S. degree in computer engineering with high honors and the M.S. degree in electrical and computer engineering from the Georgia Institute of Technology, in 2003 and 2005, respectively.
He is currently a Research Assistant at Georgia Tech and is also pursuing the Ph.D. degree. His primary area of interest is high-speed digital test and high- performance electronic systems design. He has published numerous refereed and invited publications that include conference and workshop proceedings.