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Case Study: A Complete Testing Methodology For KGD in SiP
Chiate Lin, Inapac Technology, Inc.
SiPs that combine KGD DRAM die with logic chips (ASICs) face some unique challenges in product testing. The challenges arise due to the fundamental differences in testing methodologies between DRAMs and logic devices. A testing methodology for SiPs must comprehend efficiencies at all points in the lifecycle of the product. It must include cost effective screening at the wafer level, as well as final testing of the SiP device to ensure high quality and reliability. Moreover, the methodology should allow flexibility in making intelligent tradeoffs in testing costs as the SiP product volumes increase.
Inapac has developed its SiPFLOWTM methodology that is comprehensive and cost effective for high volume SiP production. In the last KGD conference, Inapac presented a paper on its DFT approach for DRAMs, including VIBETM (Voltage Induced Burn-in Emulation) technology to replace burn-in at the wafer level.
In this paper, Inapac will present a case study on its methodology using actual production test data. The study covers SiP qualification results (Inapac's SiPLINKTM final test) of over 5 Million production units. The SiP is for a cell phone application, using Inapac's in 16Mbit DRAM IP.
Chiate M. Lin joined Inapac in 2003 as its Corporate Reliability Manager. He is responsible for ensuring Inapac's products meet or exceed customers' quality and reliability expectations. Before Inapac Technology, he held the position of Technology Manager at Magis Networks and is responsible for its foundry operations from 2001 to 2003.
Prior to Magis, Chiate was a Senior Foundry Engineer at Qualcomm CDMA Technologies (QCT) from 1997 to 2001 working with IBM Microelectronics and TSMC on RFICs and digital baseband ASICs. He received his Bachelor of Science degree in Electrical Engineering (device physics and material science) from University of California, San Diego in 1993.