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Direct Die Contacting: Towards "Known-Good-Die" for RF and Mixed-Signal
Philippe Cauvet, Philips Semiconductors
The emergence of System-in-Package products creates new big challenges for the test community, but also many opportunities for the development of advanced test techniques. The KGD requirement is one of the enablers, because a low final test yield is a killer for SiPs used in consumer applications. Although some structural test methods are now available for RF/MS dies, at-speed testing represents the best solution for achieving KGD.
In this presentation, we briefly describe a new technology for integrating passive components in a SiP, called silicon-based SiP (sbSiP). Then, we propose a solution for improving the test coverage of RF dies used in sbSiPs. This solution consists in combining a membrane probe card with a passive die. Thus, we can shorten the connections between the die under test and the components, reducing the parasitic effects, such as serial inductance and coupling capacitors. The simulation of the test fixture is also more accurate, leading to increasingly predictive results at the early phase of the test development, when debugging a new test board. Another advantage is an easy reproduction of the test environment, which is very close to the application conditions.
Finally, some results of a real-life product are shown to demonstrate the reliability of the technology.
We conclude by giving a list of further works to go towards Known-Good-Die.
Philippe Cauvet graduated as an Engineer in Physics-Instrumentation from the Conservatoire National des Arts et Métiers, France, 1989. He has been working with Philips Semiconductors for 24 years, and is now the Test Manager of the Silicon-Based SiP Program, after 15 years dedicated to Data Converters and Digital testing. A member of several international working groups, he is also in charge of the technical co-operation with public research in test technologies and methods. His main hobbies are: singing, guitar and playing golf.