Previous Workshops: 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007
Complete Path Delay Solution for High Reliability Test Screening
Glenn Bedal, Medtronic, Inc.
This paper will document a complete for delay path testmode implementation, path extraction, path analysis, scan vector generation, characterization, and failure analysis flow for high reliability circuits. This path delay testing is generated using 1149.1 JTAG structures, standard scan-based ATPG tools, and industry available low cost test systems.
The flow will focus on addressing all true paths in the design versus just taking the critical timing path approach only targeting quality yield issues. High volume product manufacturers have driven yield as the important target for path delay fault testing in order to reduce cost. However, there is a reliability issue with delay-type defects that is not being correctly considered by the industry. By looking at delay faults from a reliability concern and through characterization we are able to defect defects that exist on paths that are significantly less then the functional clock frequency. This will detect many defects that have been shown to cause reliability issues.
Glenn Bedal currently works at Medtronic supporting DFT tools and methods. He received a BSEE from Northern Arizona University in December, 1991. From January, 1992 to July, 1997 he worked in Product Development at Intel Corporation supporting DFM/Yield improvements, DFT, and test development/release for products in embedded controller division.