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DRAM Design for KGD - The "2T" Architecture
Daniel Loughmiller, Micron Technology, Inc.
Due to the inherent analog nature of traditional 1T1C (or 1T for short) DRAM technology, most KGD efforts are directed towards wafer-level testing and stress modes to enable KGD capability. However, there are architectural methods that have been proven to provide similar KGD capability.
One such DRAM architecture, referred to herein as the “2T” architecture, provides an enhanced differential sensing margin by utilizing complementary storage elements for a given logical address. The increased sensing margin allows the device to be immune or impervious to most faults and defects, thereby reducing the amount of testing or stressing required to achieve targeted DPM and FIT rates.
Using Micron’s highly successful 64Mb PSRAM KGD as a case study, this presentation will provide further discussion on what the “2T” architecture is and how it is implemented using standard DRAM technology. It will also examine early life failure rate data comparisons between 2T architecture and 1T architecture as well as other 2T architectural advantages.
Dan Loughmiller joined Micron Technology in 1990 and now works as a Product Engineering Manager for the Mobile Memory Products Group. In his current position, Dan is responsible for the development of new mobile memory devices including PSRAM and LP-SDRAM. He holds a bachelor's degree in electrical engineering from Southern Illinois University and has 39 semiconductor-related U.S. patents.