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Chip Interface Solution for High Performance SiP
B. Y. Kim, Samsung Electronics Co.
Design and Test Issues of SiP Interface Solution for Logic & Memory Die Integration is presented, and especially High Speed IOs Interface is studied with 533MHz Application Processor SiP. Conventional IO for chip to chip interface has been desinged and verified with IO IBIS or SPICE simulation. The above method is very useful for system board-level environment or limited application, but can be painful for integrating chips for high performance SiP, since the reduced R,L,C can deliver unexpected signal interference between chip to chip on SiP. A new modelling for SiP interface to duplicate SSN interactions between Logic and Memory IOs is implemented on a new SiP design tool and verified in correlation with ATE measurement.
Byeongyun (B. Y.) Kim is Principal Engineer of Operation for Mobile product test and engineering, especially in charge of SiP technology development. From 1997 to 2002, he worked for the high performance CPU development as Product Engineering Leader. From 1984 to 1997, he worked as Memory Design Engineer and also managed new memory product planning & enabling. He has about 40 patents, including 10 world-wide patents in Semiconductor Design, Test, & Package.