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Schematic Based Chip-Package-Codesign-Flow for a 7-Die SiP
Thomas Brandtner, Infineon Technologies
Modern SiP designs that contain several dies lead to more and more complex package substrate layouts. Prior to layout development the package connectivity must be specified in a package netlist consisting of thousands of entries. Hence EDA support is needed to ensure the correctness of this netlist and to provide easy interfaces between chip and package design flows.
Therefore, a schematic-based solution for a chip-package codesign flow has been implemented. It offers an easy-to-use schematic entry of the package netlist which gives an excellent overview of the proposed package connectivity. The netlist and all the die footprints may be exchanged easily with the package layout tool. Furthermore, a package layout-versus-schematic (LVS) check is provided. The electrical parasitics of the resulting package interconnects have been extracted, backannotated to system testbench schematics and simulated with an analog SPICE simulator. The exploitation of such a design flow enables the development of a correct and optimized package for a complex SiP design.
Thomas Brandtner was born in Salzburg, Austria, in 1974. He received the Dipl.-Ing. degree in Telematics (mixture of electrical engineering and computer science) from the Graz University of Technology, Austria, in 1998 and the PhD-degree in computer science from the University Linz, Austria in 2004.
He has been with Infineon Technologies since 2000, where he first focused on modeling and simulation of parasitic effects like substrate coupling in mixed-signal integrated circuits. Later he dealt with quality assurance of device models and design-for-yield concepts for deep-sub-micron CMOS technologies. Currently he is responsible for the development of a chip-package codesign flow with an emphasis on analog and mixed-signal cosimulation for complex SiP designs.