Previous Workshops: 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007
Message from the General Chair
System-in-Package (SiP) solutions using die stacking and flip-chip, and wafer-level chip-size-packages (WLCSP) offer significant advantages to designers of space-constrained systems and are increasingly the packaging solution of choice within the mobile and consumer electronics markets. Taking the theme Design Success: KGD Starts at the Beginning , the 2005 KGD Packaging & Test Workshop seeks to provide insight into how the use of known good die affects the entire manufacturing flow. Technical presentations will focus on emerging tools, processes and methods that enable successful implementation of system-in-package and other die products solutions in today's products.
In addition to the technical program, the DPC will offer free pre-workshop tutorials focusing on SiP design, 3D packaging, and known-good-die test strategies presented by leading experts in the field. An exhibition and abundant networking opportunities at the workshop's engaging social events round out the workshop experience.
As in past years, the workshop will bring together leading practitioners world-wide to share knowledge on business practices and market outlooks, and provide in-depth analysis of technologies that address the unique challenges for advanced packaging today.
I hope you will join us this September in the beautiful Napa Valley.
Eef Bagerman
Senior Director ATO Innovation
Assembly and Test Operations, Philips Semiconductors
General Chair of the 12th Annual KGD Packaging & Test Workshop