Previous Workshops: 2001 | 2002 | 2003 | 2004 | 2005 | 2006 | 2007
2005 KGD Packaging & Test Workshop Program
Pre-Workshop Tutorials
Tutorial 1: System-in-Package Design
Instructor: Bill McCaffrey, Cadence Design Systems
Abstract | Presentation PDF
Tutorial 2: 3D Packaging
Instructor: Marcos Karnezos, STATS ChipPAC
Abstract | Presentation PDF
Tutorial 3: Known-Good-Die Test Strategies
Anton Chichkov, AMI Semiconductor
Abstract | Presentation PDF
Session 1: Worldwide Activities
Session Chairs: Bill Price, Philips Semiconductors & Kazu Nakajima, K-NETS Consulting
Keynote Address
Joe Adam, Skyworks, Inc.
Abstract | Presentation PDF
Worldwide Perspective on SiP Markets
Linda Matthew, TechSearch International
Abstract | Presentation PDF
Advanced Packaging Technology Seen in Recent Cellular Phones
Howard Curtis, Portelligent
Larry Gilg, Die Products Consortium
Abstract | Presentation PDF
Advanced Packaging Trends in Europe
Francisco J. Ibañez, European Commission DG IST,
and Georg Meyer-Berg (presenter), Infineon Technologies
Abstract | Presentation PDF
Bare Die Assembly Factory Situation in China for Consumer Products
Tetsuya Onishi, G.J. Technologies
Abstract | Presentation PDF
Session 2: KGD Technologies
Session Chairs: Jim Rates, Chip Supply, Inc. & Greg May, Delphi Corporation
Design Approach to Eliminate the Influence of Alpha Particle Flux from Pb-Sn Solder in Flip-Chip Interconnects
Nita Schubert, Universidad Michoacana San Miguel de Hidalgo
Vivek Dutta, Advenient Technology
Abstract | Presentation PDF
Plasma Surface Modification Technology for Underfill Process
Masaru Nonomura, Panasonic Factory Solutions Co., Ltd.
Abstract | Presentation PDF
Advanced COB Flip Chip Interconnect by ACF (Anisotropic Conductive Film)
Tatsuo Nagamatsu, Sony Chemical
Abstract | Presentation PDF
Methodology to Skip the Memory Test Using ASB (At Speed Board)
Young Dae Kim, Samsung Electronics Co. LTD
Abstract | Presentation PDF
Testing Integrated Pressure Sensors on Wafer Level
Andreas Reithofer, Infineon Technologies
Abstract | Presentation PDF
Wafer Disposition at E-Test via Engineered Rules
Jerry Secrest, Secrest Research
Abstract | Presentation PDF
Session 3: Assembly
Session Chairs: Curtis Zwenger, Amkor & Alessandro Gandelli, Politecnico Di Milano
Low Cost High Speed Handling of Nano Components
Charles Gutentag, Tempo Electronics
Abstract | Presentation PDF
Mounting Technology for Microchips in Cell Phones and Key Devices: Working to Reduce Substrate Costs
Tom Baggio, Panasonic Factory Solutions Co. of America
Abstract | Presentation PDF
SEMI E142 for Inkless Assembly and Traceability
Dave Huntley, Kinesys Software
Abstract | Presentation PDF
Challenges in Flip Chip Die Sorting and Handling
Gerald Steinwasser, Muhlbauer, Inc.
Abstract | Presentation PDF
RFID Die Assembly Technology Trends
Tetsuya Onishi, G.J. Technologies
Abstract | Presentation PDF
Recent Assembly Process Technology to Achieve the 9 Stacked MCP
Yuichi Nagahiro, Toshiba
Presentation PDF
Session 4: KGD and SiP Test
Session Chairs: Jody Van Horn, IBM & Richard Palys, Qualcomm
A 5Gbps Stand-Alone Miniature Wafer-Level TesterAshraf Majid, Georgia Institute of Technology
Abstract | Presentation PDF
Case Study: A Complete Testing Methodology For KGD in SiPs
Chiate Lin, Inapac Technology, Inc.
Abstract | Presentation PDF
SureCHIP™, The Ultimate in KGD Testing
Rick Pierson, International Rectifier
Abstract | Presentation PDF
Direct Die Contacting: Towards "Known-Good-Die" for RF and Mixed-Signal
Philippe Cauvet, Philips Semiconductors
Abstract | Presentation PDF
Complete Path Delay Solution for High Reliability Test Screening
Glenn Bedal, Medtronic, Inc.
Abstract | Presentation PDF
Multi-site Test with Full Diagnosis Support
Peter Muhmenthaler, Infineon Technologies
Abstract | Presentation PDF
RF BIST (Built-In Self-Test) Scheme for Low Noise Amplifier (LNA) in RF Systems
Bruce Kim, University of Alabama
Abstract | Presentation PDF | Paper PDF
Session 5: SiP-Enabling Technologies
Session Chairs: Bob Sullivan, HDPUG & Tetsuya Onishi, GJ Technology
DRAM Design for KGD – The “2T” Architecture
Daniel Loughmiller, Micron Technology, Inc.
Abstract | Presentation PDF
Silicon/Substrate Passive Integration
Alain Rougier, Philips Semiconductors
Abstract | Presentation PDF
Chip Interface Solution for High Performance SiP
B. Y. Kim, Samsung Electronics Co.
Abstract | Presentation PDF
The Early Stage Application of 3D LSI Stacking Technology -- ZyCube CSP for CMOS Image Sensor
Manabu Bonkohara, ZyCube
Abstract | Presentation PDF
Thinned Wafer Stress Relief
Christopher Mielke, BKM Technology Partners
Abstract | Presentation PDF
Wafer Level Die Marking and Substrate Mapping Standards
Aidan Cunningham, GSI Lumonics
Abstract | Presentation PDF
Session 6: Co-Design for SiP
Session Chairs: Georg Meyer-Berg, Infineon Technologies & Bruce Kim, Alabama University
Standards for Procurement and Use of Die Devices
Mike Roughton, MGR Consultants
Abstract | Presentation PDF
The Impact of KGD Probability on Stacked-Die Yield and Cost
Harry K. Charles, Jr., The Johns Hopkins University Applied Physics Laboratory
Abstract | Presentation PDF
Schematic Based Chip-Package-Codesign-Flow for a 7-Die SiP
Thomas Brandtner, Infineon Technologies
Abstract | Presentation PDF
Built-in-Test Solutions for SiP
Philippe Cauvet, Philips Semiconductors
Abstract | Presentation PDF
System Integration Using System in Package Technology – The Need for Co-Design
Stan Mihelcic, LSI Logic
Abstract | Presentation PDF