Test Challenges for Mobile Application SiP

Byeongyun (BY) Kim, Samsung Electronics

The presentation describes the overall consideration for SiP test development, and explores the test challenges for Mobile Application SiP (MASiP) which integrates Memory, Analog, RF Chips, and High Speed CPUs into a penny.

Test and Verification for MASiP requires handling not only individual chips but also packaging interconnection impact between integrated chips, since a subtle change as like power bounce or signal coupling on analog or high speed connectivity can cause easily detrimental failures of MASiP. Therefore, test is getting complicated in proportion to increasing number of integrated chips to clear uncertainty of chip-to-chip operation, leading to very time consuming work.

The presentation will handle test challenges for cost effective and quality-enhanced test flow of MASiP, and introduce new approach to reduce test complexity with scenario based test plan. And, finally, low cost test flow will be highlighted.

Principal Engineer of Operation for Mobile product test and engineering, especially in charge of SiP technology enabling & development. From 1997 to 2002, he worked for high performance CPU development as Product Engineering Leader. From 1984 to - 1997, he worked as Memory Design Engineer and also managed new memory product planning & enabling. He has over 40 patents, including 10 patents in Semiconductor Design, Test, & Package.