3D/SiP Key Technologies

Tetsuya Onishi, Grand Joint Technology Ltd.

This presentation will discuss the future direction & the trend of 3D / SiP(System-in-package ) technology and related key process technologies.

The system-in-package typically contains two to six chips at most, and generally uses a laminate. The current generation of SiP requirements, combined with continued focus on the tight space requirement for light weight, portable applications. This presentation will highlight the key process technology & material that must be addressed to SiP performance.

Thin wafer technology is one of important issue of SiP, and stress relief offers the advantages of increasing the strength of the die. We'd like to discuss of the method of thin wafer, stress relief & dicing technology. This presentation will also show several stacked die key technologies, material detail for high performance 3D / SiP, and new Si through technology topics from Japan JIEP ICEP 06.

Onishi Tetsuya is managing director of Grand Joint Technology Ltd (G.J.Tech). Formed in Hong Kong in 1997, Grand Joint Technology Ltd. (G.J.Tech) is a microelectronics assembly process consulting company involved in Materials, Design, Process, and Analysis for Bare die product, COB, SMT, Packaging and LCD Modules.

Onishi Tetsuya received the " Die Products Industry Achievement award " at the 8th Annual International KGD Packaging and Test Workshop, held on September 9 through 12, 2001 in Napa, California.