Recent Advances in Low-Cost Multi-GHz Test

David Keezer, Georgia Institute of Technology

In this paper we provide a summary and update for 3 on-going research projects. Each project is developing low-cost methods and circuits to help meet the demanding test requirements of multi-GHz circuits and systems. These techniques are sufficiently general that they should be of interest to a wide range of testing professionals at the workshop. In one project, we develop a simplified yet high-performance “mini tester” for at-speed functional test and support of BIST at the wafer-probe level. In this presentation we will demonstrate the test system at 8 Gbps. In a second project, we use FPGA-based test architecture to produce multiple multi-GHz signals for evaluating the performance of an optical switching network (called “Data Vortex”). The current system is demonstrated at rates up to 4Gbps which is even beyond the nominal 2.5 Gbps data rate of the network. We are currently developing a network interface card (NIC) to provide a link between the DV and a standard PCIexpress port. In a third project, we are developing (together with engineers at IBM), several test modules that can be added to standard automated test systems to provide economical testing at 2.5 Gbps and above. We will demonstrate several new test functions in the 2.5Gbps to 6.4Gbps range.

Dr. Keezer is a Professor of Electrical and Computer Engineering at Georgia Tech. His research focuses on the design and test of high-performance electronic systems. He has published over 150 articles on electronics testing. Prior to joining Georgia Tech in 1995, Dr. Keezer was an Associate Professor at the University of South Florida. Dr. Keezer has worked for Harris Corp., Intel Corp., and IBM Corp.. He received the Ph.D. from Carnegie-Mellon Univ., the M.S. from Caltech, and the B.S. from the University of California at Berkeley. He also has an MBA from the Florida Institute of Technology. Dr. Keezer is a Senior Member of the IEEE.