Copper Pillar Well Methodology and Implementation in a VLP FB-DIMM

Peter Salmon, Peter Salmon, LLC.

A new concept for fabricating very low profile fully-buffered dual in line memory modules is proposed. Interconnection layers are built up on copper panels using high resolution photolithography available on current fabrication equipment. The copper substrate provides a built-in heat spreader and superior thermal performance. 4-high or 8-high die stacks are employed. A new Copper-Pillar-Well (CPW) flip chip connector is used; it provides convenient assembly, testing, and rework of all 72 or 144 memory chips in each module without melting any solder. The same connectors enable the Advanced Memory Buffer (AMB) chip to be attached within the height limitation of 18.3mm for the VLP module. Improved electrical, thermal and mechanical properties are potentially achievable, enabling 8-16 GByte modules having advanced specifications.

Peter is an inventor with a background in IC chip design, systems engineering, and electrostatic printing. He holds three degrees in Electrical Engineering from Auckland University, New Zealand, and Northeastern University in Boston. He is currently working on advanced packaging techniques, an electrostatic motor, and new electronic printing methods.