2008 Program > Technical Sessions
2008 Advance Technical Program
Please note that the advance program only lists presentations confirmed at this time and is subject to change.
Session 2: Test Infrastructure
Session 1: Special Topics
Monday, September 8, 2008
9:00am - 12:00pm
Keynote Address
Mario Bolanos-Avila, Texas Instruments
Saving Energy with Advanced Power Semiconductors
Dean Henderson, Infineon Technologies
High Power LEDs for Solid State Lighting: Status, Trends, and Challenges
Bob Steward, Philips LumiLeds Lighting Company
Session 2: Test Infrastructure
Monday, September 8, 2008
1:30pm - 5:00pm
Probing for Known Good Die
Rob Marcelis, Salland Engineering
BGA/CSP, LGA/QFN Test Solutions & Interconnect Technology with SPIRAL CONTACT™
Scott Hirai, Advanced Systems Japan, Inc.
Super Sockets - Integrating Technology - Test Board to Socket
Thomas Bresnan, R&D Circuits
Introduce Burn-in and Final Test Socket with Spiral Contact
Shin Yoshida, ALPS Electric Co, LTD
Wafer Level and KGD Test for Power Devices
Don Feuerstein, SemiProbe
Fault Counting Standardization
Rohit Kapur, Synopsis, Inc.
Session 3: KGD Engineering
Tuesday, September 9, 2008
9:00am - 12:00pm
Dry Polishing of Wide Band-gap Semiconductor Wafers
Scott Sullivan, Disco Hi-Tec America
Enabling Technologies for Differentiated End Products
Dean Henderson, Infineon Technologies
Ultra-Thin Chip Manufacturing for New Packages
Peter Heinze, PVA TePla AG
When Known Good Die Go Bad: The Power of Failure Analysis
Tom Weldon, Micron
Intelligent - not Total Recall
Dave Huntley, Kinesys Software
Session 4: Test Methods
Tuesday, September 9, 2008
1:00pm - 3:00pm
A New WBI DOE Methodology to break through High BurnIn Power Consumption in Nano & Giga Era
Gibum Koo, Samsung Electronics
Semiconductor Test: From Back-End To Center Stage
Bill Price, Optimal Test
Strategies for Low-cost Testing Above 10 Gbps
David Keezer, Georgia Institute of Technology
Robustness Validation - A New Strategy for Automotive Semiconductor Quality
Peter Wilson, ON Semiconductor
Session 5: Advanced Packaging
Wednesday, September 10, 2008
9:00am - 12:00pm
Overview of the FC and WLP market
Jan Vardaman, Techsearch International
Requirements for Cost-Effective 3D Integration
Philip Pieters, IMEC
Chip-Stacking for TSV
Jim Repko, AJI Technologies
Chip In Wafer for Integrated System
Jean-Charles Souriau, CEA-LETI Minatec
KGDs and Embedded Substrates Join Hands to Drive Cost & Form-Factor in Mobile Applications
Arun Amirtham, NXP Semiconductors
Die Products Embedded Component Trend
Tetsuya Onishi, Grand Joint Technology, Ltd.